Lines Matching full:qspi
3 * Microchip coreQSPI QSPI controller driver
25 * QSPI Control register mask defines
43 * QSPI Frames register mask defines
55 * QSPI Interrupt Enable register mask defines
65 * QSPI Status register mask defines
84 /* QSPI ready time out value */
88 * QSPI Register offsets.
103 * struct mchp_coreqspi - Defines qspi driver instance
104 * @regs: Virtual address of the QSPI controller registers
105 * @clk: QSPI Operating clock
126 static int mchp_coreqspi_set_mode(struct mchp_coreqspi *qspi, const struct spi_mem_op *op) in mchp_coreqspi_set_mode() argument
128 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_set_mode()
139 * 1: 4-bits (QSPI) in mchp_coreqspi_set_mode()
156 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_set_mode()
161 static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) in mchp_coreqspi_read_op() argument
165 if (!qspi->rx_len) in mchp_coreqspi_read_op()
168 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
175 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
177 while (qspi->rx_len >= 4) { in mchp_coreqspi_read_op()
178 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) in mchp_coreqspi_read_op()
180 data = readl_relaxed(qspi->regs + REG_X4_RX_DATA); in mchp_coreqspi_read_op()
181 *(u32 *)qspi->rxbuf = data; in mchp_coreqspi_read_op()
182 qspi->rxbuf += 4; in mchp_coreqspi_read_op()
183 qspi->rx_len -= 4; in mchp_coreqspi_read_op()
187 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_read_op()
189 while (qspi->rx_len--) { in mchp_coreqspi_read_op()
190 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_RXFIFOEMPTY) in mchp_coreqspi_read_op()
192 data = readl_relaxed(qspi->regs + REG_RX_DATA); in mchp_coreqspi_read_op()
193 *qspi->rxbuf++ = (data & 0xFF); in mchp_coreqspi_read_op()
197 static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi, bool word) in mchp_coreqspi_write_op() argument
201 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_write_op()
203 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_op()
205 while (qspi->tx_len >= 4) { in mchp_coreqspi_write_op()
206 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) in mchp_coreqspi_write_op()
208 data = *(u32 *)qspi->txbuf; in mchp_coreqspi_write_op()
209 qspi->txbuf += 4; in mchp_coreqspi_write_op()
210 qspi->tx_len -= 4; in mchp_coreqspi_write_op()
211 writel_relaxed(data, qspi->regs + REG_X4_TX_DATA); in mchp_coreqspi_write_op()
215 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_write_op()
217 while (qspi->tx_len--) { in mchp_coreqspi_write_op()
218 while (readl_relaxed(qspi->regs + REG_STATUS) & STATUS_TXFIFOFULL) in mchp_coreqspi_write_op()
220 data = *qspi->txbuf++; in mchp_coreqspi_write_op()
221 writel_relaxed(data, qspi->regs + REG_TX_DATA); in mchp_coreqspi_write_op()
225 static void mchp_coreqspi_enable_ints(struct mchp_coreqspi *qspi) in mchp_coreqspi_enable_ints() argument
231 writel_relaxed(mask, qspi->regs + REG_IEN); in mchp_coreqspi_enable_ints()
234 static void mchp_coreqspi_disable_ints(struct mchp_coreqspi *qspi) in mchp_coreqspi_disable_ints() argument
236 writel_relaxed(0, qspi->regs + REG_IEN); in mchp_coreqspi_disable_ints()
241 struct mchp_coreqspi *qspi = (struct mchp_coreqspi *)dev_id; in mchp_coreqspi_isr() local
243 int intfield = readl_relaxed(qspi->regs + REG_STATUS) & STATUS_MASK; in mchp_coreqspi_isr()
249 writel_relaxed(IEN_TXDONE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
254 writel_relaxed(IEN_RXAVAILABLE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
255 mchp_coreqspi_read_op(qspi); in mchp_coreqspi_isr()
260 writel_relaxed(IEN_RXDONE, qspi->regs + REG_STATUS); in mchp_coreqspi_isr()
261 complete(&qspi->data_completion); in mchp_coreqspi_isr()
268 static int mchp_coreqspi_setup_clock(struct mchp_coreqspi *qspi, struct spi_device *spi) in mchp_coreqspi_setup_clock() argument
273 clk_hz = clk_get_rate(qspi->clk); in mchp_coreqspi_setup_clock()
285 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_clock()
288 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_clock()
289 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_clock()
296 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_clock()
304 struct mchp_coreqspi *qspi = spi_controller_get_devdata(ctlr); in mchp_coreqspi_setup_op() local
305 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_op()
309 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_setup_op()
314 static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const struct spi_mem_op *op) in mchp_coreqspi_config_op() argument
352 writel_relaxed(frames, qspi->regs + REG_FRAMESUP); in mchp_coreqspi_config_op()
360 ctrl = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_config_op()
366 writel_relaxed(frames, qspi->regs + REG_FRAMES); in mchp_coreqspi_config_op()
371 struct mchp_coreqspi *qspi = spi_controller_get_devdata in mchp_qspi_wait_for_ready() local
376 ret = readl_poll_timeout(qspi->regs + REG_STATUS, status, in mchp_qspi_wait_for_ready()
381 "Timeout waiting on QSPI ready.\n"); in mchp_qspi_wait_for_ready()
390 struct mchp_coreqspi *qspi = spi_controller_get_devdata in mchp_coreqspi_exec_op() local
397 mutex_lock(&qspi->op_lock); in mchp_coreqspi_exec_op()
402 err = mchp_coreqspi_setup_clock(qspi, mem->spi); in mchp_coreqspi_exec_op()
406 err = mchp_coreqspi_set_mode(qspi, op); in mchp_coreqspi_exec_op()
410 reinit_completion(&qspi->data_completion); in mchp_coreqspi_exec_op()
411 mchp_coreqspi_config_op(qspi, op); in mchp_coreqspi_exec_op()
413 qspi->txbuf = &opcode; in mchp_coreqspi_exec_op()
414 qspi->rxbuf = NULL; in mchp_coreqspi_exec_op()
415 qspi->tx_len = op->cmd.nbytes; in mchp_coreqspi_exec_op()
416 qspi->rx_len = 0; in mchp_coreqspi_exec_op()
417 mchp_coreqspi_write_op(qspi, false); in mchp_coreqspi_exec_op()
420 qspi->txbuf = &opaddr[0]; in mchp_coreqspi_exec_op()
423 qspi->txbuf[i] = address >> (8 * (op->addr.nbytes - i - 1)); in mchp_coreqspi_exec_op()
425 qspi->rxbuf = NULL; in mchp_coreqspi_exec_op()
426 qspi->tx_len = op->addr.nbytes; in mchp_coreqspi_exec_op()
427 qspi->rx_len = 0; in mchp_coreqspi_exec_op()
428 mchp_coreqspi_write_op(qspi, false); in mchp_coreqspi_exec_op()
433 qspi->txbuf = (u8 *)op->data.buf.out; in mchp_coreqspi_exec_op()
434 qspi->rxbuf = NULL; in mchp_coreqspi_exec_op()
435 qspi->rx_len = 0; in mchp_coreqspi_exec_op()
436 qspi->tx_len = op->data.nbytes; in mchp_coreqspi_exec_op()
437 mchp_coreqspi_write_op(qspi, true); in mchp_coreqspi_exec_op()
439 qspi->txbuf = NULL; in mchp_coreqspi_exec_op()
440 qspi->rxbuf = (u8 *)op->data.buf.in; in mchp_coreqspi_exec_op()
441 qspi->rx_len = op->data.nbytes; in mchp_coreqspi_exec_op()
442 qspi->tx_len = 0; in mchp_coreqspi_exec_op()
446 mchp_coreqspi_enable_ints(qspi); in mchp_coreqspi_exec_op()
448 if (!wait_for_completion_timeout(&qspi->data_completion, msecs_to_jiffies(1000))) in mchp_coreqspi_exec_op()
452 mutex_unlock(&qspi->op_lock); in mchp_coreqspi_exec_op()
453 mchp_coreqspi_disable_ints(qspi); in mchp_coreqspi_exec_op()
504 struct mchp_coreqspi *qspi; in mchp_coreqspi_probe() local
509 ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); in mchp_coreqspi_probe()
512 "unable to allocate host for QSPI controller\n"); in mchp_coreqspi_probe()
514 qspi = spi_controller_get_devdata(ctlr); in mchp_coreqspi_probe()
515 platform_set_drvdata(pdev, qspi); in mchp_coreqspi_probe()
517 qspi->regs = devm_platform_ioremap_resource(pdev, 0); in mchp_coreqspi_probe()
518 if (IS_ERR(qspi->regs)) in mchp_coreqspi_probe()
519 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->regs), in mchp_coreqspi_probe()
522 qspi->clk = devm_clk_get_enabled(&pdev->dev, NULL); in mchp_coreqspi_probe()
523 if (IS_ERR(qspi->clk)) in mchp_coreqspi_probe()
524 return dev_err_probe(&pdev->dev, PTR_ERR(qspi->clk), in mchp_coreqspi_probe()
527 init_completion(&qspi->data_completion); in mchp_coreqspi_probe()
528 mutex_init(&qspi->op_lock); in mchp_coreqspi_probe()
530 qspi->irq = platform_get_irq(pdev, 0); in mchp_coreqspi_probe()
531 if (qspi->irq < 0) in mchp_coreqspi_probe()
532 return qspi->irq; in mchp_coreqspi_probe()
534 ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr, in mchp_coreqspi_probe()
535 IRQF_SHARED, pdev->name, qspi); in mchp_coreqspi_probe()
558 struct mchp_coreqspi *qspi = platform_get_drvdata(pdev); in mchp_coreqspi_remove() local
559 u32 control = readl_relaxed(qspi->regs + REG_CONTROL); in mchp_coreqspi_remove()
561 mchp_coreqspi_disable_ints(qspi); in mchp_coreqspi_remove()
563 writel_relaxed(control, qspi->regs + REG_CONTROL); in mchp_coreqspi_remove()
583 MODULE_DESCRIPTION("Microchip coreQSPI QSPI controller driver");