Lines Matching +full:tx +full:- +full:clk +full:- +full:10 +full:- +full:inverted
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 #include <linux/clk.h>
10 #include <linux/dma-mapping.h>
26 #include <linux/dma/imx-dma.h>
100 struct clk *clk_per;
101 struct clk *clk_ipg;
109 void (*tx)(struct spi_imx_data *spi_imx); member
113 unsigned int txfifo; /* number of words pushed in tx FIFO */
133 return d->devtype_data->devtype == IMX27_CSPI; in is_imx27_cspi()
138 return d->devtype_data->devtype == IMX35_CSPI; in is_imx35_cspi()
143 return d->devtype_data->devtype == IMX51_ECSPI; in is_imx51_ecspi()
148 return d->devtype_data->devtype == IMX53_ECSPI; in is_imx53_ecspi()
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
156 if (spi_imx->rx_buf) { \
157 *(type *)spi_imx->rx_buf = val; \
158 spi_imx->rx_buf += sizeof(type); \
161 spi_imx->remainder -= sizeof(type); \
169 if (spi_imx->tx_buf) { \
170 val = *(type *)spi_imx->tx_buf; \
171 spi_imx->tx_buf += sizeof(type); \
174 spi_imx->count -= sizeof(type); \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
238 if (!use_dma || controller->fallback) in spi_imx_can_dma()
241 if (!controller->dma_rx) in spi_imx_can_dma()
244 if (spi_imx->target_mode) in spi_imx_can_dma()
247 if (transfer->len < spi_imx->devtype_data->fifo_size) in spi_imx_can_dma()
250 spi_imx->dynamic_burst = 0; in spi_imx_can_dma()
259 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap_u32()
311 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap_u32()
315 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_rx_swap_u32()
321 *(u32 *)spi_imx->rx_buf = val; in spi_imx_buf_rx_swap_u32()
322 spi_imx->rx_buf += sizeof(u32); in spi_imx_buf_rx_swap_u32()
325 spi_imx->remainder -= sizeof(u32); in spi_imx_buf_rx_swap_u32()
333 unaligned = spi_imx->remainder % 4; in spi_imx_buf_rx_swap()
340 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_rx_swap()
345 val = readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_buf_rx_swap()
347 while (unaligned--) { in spi_imx_buf_rx_swap()
348 if (spi_imx->rx_buf) { in spi_imx_buf_rx_swap()
349 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff; in spi_imx_buf_rx_swap()
350 spi_imx->rx_buf++; in spi_imx_buf_rx_swap()
352 spi_imx->remainder--; in spi_imx_buf_rx_swap()
363 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap_u32()
364 val = *(u32 *)spi_imx->tx_buf; in spi_imx_buf_tx_swap_u32()
365 spi_imx->tx_buf += sizeof(u32); in spi_imx_buf_tx_swap_u32()
368 spi_imx->count -= sizeof(u32); in spi_imx_buf_tx_swap_u32()
370 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_buf_tx_swap_u32()
377 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap_u32()
385 unaligned = spi_imx->count % 4; in spi_imx_buf_tx_swap()
392 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) { in spi_imx_buf_tx_swap()
397 while (unaligned--) { in spi_imx_buf_tx_swap()
398 if (spi_imx->tx_buf) { in spi_imx_buf_tx_swap()
399 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned); in spi_imx_buf_tx_swap()
400 spi_imx->tx_buf++; in spi_imx_buf_tx_swap()
402 spi_imx->count--; in spi_imx_buf_tx_swap()
405 writel(val, spi_imx->base + MXC_CSPITXDATA); in spi_imx_buf_tx_swap()
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA)); in mx53_ecspi_rx_target()
412 if (spi_imx->rx_buf) { in mx53_ecspi_rx_target()
413 int n_bytes = spi_imx->target_burst % sizeof(val); in mx53_ecspi_rx_target()
418 memcpy(spi_imx->rx_buf, in mx53_ecspi_rx_target()
419 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes); in mx53_ecspi_rx_target()
421 spi_imx->rx_buf += n_bytes; in mx53_ecspi_rx_target()
422 spi_imx->target_burst -= n_bytes; in mx53_ecspi_rx_target()
425 spi_imx->remainder -= sizeof(u32); in mx53_ecspi_rx_target()
431 int n_bytes = spi_imx->count % sizeof(val); in mx53_ecspi_tx_target()
436 if (spi_imx->tx_buf) { in mx53_ecspi_tx_target()
437 memcpy(((u8 *)&val) + sizeof(val) - n_bytes, in mx53_ecspi_tx_target()
438 spi_imx->tx_buf, n_bytes); in mx53_ecspi_tx_target()
440 spi_imx->tx_buf += n_bytes; in mx53_ecspi_tx_target()
443 spi_imx->count -= n_bytes; in mx53_ecspi_tx_target()
445 writel(val, spi_imx->base + MXC_CSPITXDATA); in mx53_ecspi_tx_target()
453 * there are two 4-bit dividers, the pre-divider divides by in mx51_ecspi_clkdiv()
454 * $pre, the post-divider by 2^$post in mx51_ecspi_clkdiv()
457 unsigned int fin = spi_imx->spi_clk; in mx51_ecspi_clkdiv()
461 post = fls(fin) - fls(fspi); in mx51_ecspi_clkdiv()
467 post = max(4U, post) - 4; in mx51_ecspi_clkdiv()
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n", in mx51_ecspi_clkdiv()
474 pre = DIV_ROUND_UP(fin, fspi << post) - 1; in mx51_ecspi_clkdiv()
476 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n", in mx51_ecspi_clkdiv()
499 writel(val, spi_imx->base + MX51_ECSPI_INT); in mx51_ecspi_intctrl()
506 reg = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
508 writel(reg, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_trigger()
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_disable()
524 return spi->controller->unused_native_cs; in mx51_ecspi_channel()
530 struct spi_device *spi = msg->spi; in mx51_ecspi_prepare_message()
535 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
540 if (spi_imx->target_mode) in mx51_ecspi_prepare_message()
548 if (spi->mode & SPI_READY) in mx51_ecspi_prepare_message()
549 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); in mx51_ecspi_prepare_message()
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_message()
560 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
561 if (spi->mode & SPI_LOOP) in mx51_ecspi_prepare_message()
565 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG); in mx51_ecspi_prepare_message()
572 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_message()
577 if (spi->mode & SPI_CPOL) { in mx51_ecspi_prepare_message()
585 if (spi->mode & SPI_MOSI_IDLE_LOW) in mx51_ecspi_prepare_message()
590 if (spi->mode & SPI_CS_HIGH) in mx51_ecspi_prepare_message()
598 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_ecspi_prepare_message()
606 * the polarity of SCLK should be inverted, the GPIO ChipSelect might in mx51_ecspi_prepare_message()
611 * Because spi_imx->spi_bus_clk is only set in prepare_message in mx51_ecspi_prepare_message()
617 list_for_each_entry(xfer, &msg->transfers, transfer_list) { in mx51_ecspi_prepare_message()
618 if (!xfer->speed_hz) in mx51_ecspi_prepare_message()
620 min_speed_hz = min(xfer->speed_hz, min_speed_hz); in mx51_ecspi_prepare_message()
624 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */ in mx51_ecspi_prepare_message()
627 usleep_range(delay, delay + 10); in mx51_ecspi_prepare_message()
635 bool cpha = (spi->mode & SPI_CPHA); in mx51_configure_cpha()
636 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; in mx51_configure_cpha()
637 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
648 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); in mx51_configure_cpha()
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
655 u32 clk; in mx51_ecspi_prepare_transfer() local
659 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx)) in mx51_ecspi_prepare_transfer()
660 ctrl |= (spi_imx->target_burst * 8 - 1) in mx51_ecspi_prepare_transfer()
663 ctrl |= (spi_imx->bits_per_word - 1) in mx51_ecspi_prepare_transfer()
670 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk); in mx51_ecspi_prepare_transfer()
671 spi_imx->spi_bus_clk = clk; in mx51_ecspi_prepare_transfer()
679 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed) in mx51_ecspi_prepare_transfer()
684 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in mx51_ecspi_prepare_transfer()
693 if (spi_imx->devtype_data->tx_glitch_fixed) in mx51_setup_wml()
694 tx_wml = spi_imx->wml; in mx51_setup_wml()
699 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) | in mx51_setup_wml()
701 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) | in mx51_setup_wml()
703 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA); in mx51_setup_wml()
708 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; in mx51_ecspi_rx_available()
715 readl(spi_imx->base + MXC_CSPIRXDATA); in mx51_ecspi_reset()
758 writel(val, spi_imx->base + MXC_CSPIINT); in mx31_intctrl()
765 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
767 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_trigger()
780 unsigned int clk; in mx31_prepare_transfer() local
782 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx31_prepare_transfer()
784 spi_imx->spi_bus_clk = clk; in mx31_prepare_transfer()
787 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT; in mx31_prepare_transfer()
790 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT; in mx31_prepare_transfer()
793 if (spi->mode & SPI_CPHA) in mx31_prepare_transfer()
795 if (spi->mode & SPI_CPOL) in mx31_prepare_transfer()
797 if (spi->mode & SPI_CS_HIGH) in mx31_prepare_transfer()
804 if (spi_imx->usedma) in mx31_prepare_transfer()
807 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx31_prepare_transfer()
809 reg = readl(spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
810 if (spi->mode & SPI_LOOP) in mx31_prepare_transfer()
814 writel(reg, spi_imx->base + MX31_CSPI_TESTREG); in mx31_prepare_transfer()
816 if (spi_imx->usedma) { in mx31_prepare_transfer()
822 spi_imx->base + MX31_CSPI_DMAREG); in mx31_prepare_transfer()
830 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; in mx31_rx_available()
836 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) in mx31_reset()
837 readl(spi_imx->base + MXC_CSPIRXDATA); in mx31_reset()
848 #define MX21_CSPICTRL_ENABLE (1 << 10)
862 writel(val, spi_imx->base + MXC_CSPIINT); in mx21_intctrl()
869 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
871 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_trigger()
885 unsigned int clk; in mx21_prepare_transfer() local
887 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk) in mx21_prepare_transfer()
889 spi_imx->spi_bus_clk = clk; in mx21_prepare_transfer()
891 reg |= spi_imx->bits_per_word - 1; in mx21_prepare_transfer()
893 if (spi->mode & SPI_CPHA) in mx21_prepare_transfer()
895 if (spi->mode & SPI_CPOL) in mx21_prepare_transfer()
897 if (spi->mode & SPI_CS_HIGH) in mx21_prepare_transfer()
902 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx21_prepare_transfer()
909 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; in mx21_rx_available()
914 writel(1, spi_imx->base + MXC_RESET); in mx21_reset()
925 #define MX1_CSPICTRL_HOST (1 << 10)
937 writel(val, spi_imx->base + MXC_CSPIINT); in mx1_intctrl()
944 reg = readl(spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
946 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_trigger()
959 unsigned int clk; in mx1_prepare_transfer() local
961 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) << in mx1_prepare_transfer()
963 spi_imx->spi_bus_clk = clk; in mx1_prepare_transfer()
965 reg |= spi_imx->bits_per_word - 1; in mx1_prepare_transfer()
967 if (spi->mode & SPI_CPHA) in mx1_prepare_transfer()
969 if (spi->mode & SPI_CPOL) in mx1_prepare_transfer()
972 writel(reg, spi_imx->base + MXC_CSPICTRL); in mx1_prepare_transfer()
979 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; in mx1_rx_available()
984 writel(1, spi_imx->base + MXC_RESET); in mx1_reset()
1107 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1108 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1109 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1110 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1111 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1112 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1113 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1114 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1123 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1125 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET); in spi_imx_set_burst_len()
1126 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); in spi_imx_set_burst_len()
1138 if (!spi_imx->remainder) { in spi_imx_push()
1139 if (spi_imx->dynamic_burst) { in spi_imx_push()
1142 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST; in spi_imx_push()
1149 spi_imx->remainder = burst_len; in spi_imx_push()
1151 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word); in spi_imx_push()
1155 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) { in spi_imx_push()
1156 if (!spi_imx->count) in spi_imx_push()
1158 if (spi_imx->dynamic_burst && in spi_imx_push()
1159 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4)) in spi_imx_push()
1161 spi_imx->tx(spi_imx); in spi_imx_push()
1162 spi_imx->txfifo++; in spi_imx_push()
1165 if (!spi_imx->target_mode) in spi_imx_push()
1166 spi_imx->devtype_data->trigger(spi_imx); in spi_imx_push()
1173 while (spi_imx->txfifo && in spi_imx_isr()
1174 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_isr()
1175 spi_imx->rx(spi_imx); in spi_imx_isr()
1176 spi_imx->txfifo--; in spi_imx_isr()
1179 if (spi_imx->count) { in spi_imx_isr()
1184 if (spi_imx->txfifo) { in spi_imx_isr()
1188 spi_imx->devtype_data->intctrl( in spi_imx_isr()
1193 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_isr()
1194 complete(&spi_imx->xfer_done); in spi_imx_isr()
1203 struct dma_slave_config rx = {}, tx = {}; in spi_imx_dma_configure() local
1206 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) { in spi_imx_dma_configure()
1217 return -EINVAL; in spi_imx_dma_configure()
1220 tx.direction = DMA_MEM_TO_DEV; in spi_imx_dma_configure()
1221 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA; in spi_imx_dma_configure()
1222 tx.dst_addr_width = buswidth; in spi_imx_dma_configure()
1223 tx.dst_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1224 ret = dmaengine_slave_config(controller->dma_tx, &tx); in spi_imx_dma_configure()
1226 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1231 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA; in spi_imx_dma_configure()
1233 rx.src_maxburst = spi_imx->wml; in spi_imx_dma_configure()
1234 ret = dmaengine_slave_config(controller->dma_rx, &rx); in spi_imx_dma_configure()
1236 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret); in spi_imx_dma_configure()
1246 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_setupxfer()
1251 if (!t->speed_hz) { in spi_imx_setupxfer()
1252 if (!spi->max_speed_hz) { in spi_imx_setupxfer()
1253 dev_err(&spi->dev, "no speed_hz provided!\n"); in spi_imx_setupxfer()
1254 return -EINVAL; in spi_imx_setupxfer()
1256 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n"); in spi_imx_setupxfer()
1257 spi_imx->spi_bus_clk = spi->max_speed_hz; in spi_imx_setupxfer()
1259 spi_imx->spi_bus_clk = t->speed_hz; in spi_imx_setupxfer()
1261 spi_imx->bits_per_word = t->bits_per_word; in spi_imx_setupxfer()
1262 spi_imx->count = t->len; in spi_imx_setupxfer()
1265 * Initialize the functions for transfer. To transfer non byte-aligned in spi_imx_setupxfer()
1266 * words, we have to use multiple word-size bursts, we can't use in spi_imx_setupxfer()
1269 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode && in spi_imx_setupxfer()
1270 !(spi->mode & SPI_CS_WORD) && in spi_imx_setupxfer()
1271 (spi_imx->bits_per_word == 8 || in spi_imx_setupxfer()
1272 spi_imx->bits_per_word == 16 || in spi_imx_setupxfer()
1273 spi_imx->bits_per_word == 32)) { in spi_imx_setupxfer()
1275 spi_imx->rx = spi_imx_buf_rx_swap; in spi_imx_setupxfer()
1276 spi_imx->tx = spi_imx_buf_tx_swap; in spi_imx_setupxfer()
1277 spi_imx->dynamic_burst = 1; in spi_imx_setupxfer()
1280 if (spi_imx->bits_per_word <= 8) { in spi_imx_setupxfer()
1281 spi_imx->rx = spi_imx_buf_rx_u8; in spi_imx_setupxfer()
1282 spi_imx->tx = spi_imx_buf_tx_u8; in spi_imx_setupxfer()
1283 } else if (spi_imx->bits_per_word <= 16) { in spi_imx_setupxfer()
1284 spi_imx->rx = spi_imx_buf_rx_u16; in spi_imx_setupxfer()
1285 spi_imx->tx = spi_imx_buf_tx_u16; in spi_imx_setupxfer()
1287 spi_imx->rx = spi_imx_buf_rx_u32; in spi_imx_setupxfer()
1288 spi_imx->tx = spi_imx_buf_tx_u32; in spi_imx_setupxfer()
1290 spi_imx->dynamic_burst = 0; in spi_imx_setupxfer()
1293 if (spi_imx_can_dma(spi_imx->controller, spi, t)) in spi_imx_setupxfer()
1294 spi_imx->usedma = true; in spi_imx_setupxfer()
1296 spi_imx->usedma = false; in spi_imx_setupxfer()
1298 spi_imx->rx_only = ((t->tx_buf == NULL) in spi_imx_setupxfer()
1299 || (t->tx_buf == spi->controller->dummy_tx)); in spi_imx_setupxfer()
1301 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) { in spi_imx_setupxfer()
1302 spi_imx->rx = mx53_ecspi_rx_target; in spi_imx_setupxfer()
1303 spi_imx->tx = mx53_ecspi_tx_target; in spi_imx_setupxfer()
1304 spi_imx->target_burst = t->len; in spi_imx_setupxfer()
1307 spi_imx->devtype_data->prepare_transfer(spi_imx, spi); in spi_imx_setupxfer()
1314 struct spi_controller *controller = spi_imx->controller; in spi_imx_sdma_exit()
1316 if (controller->dma_rx) { in spi_imx_sdma_exit()
1317 dma_release_channel(controller->dma_rx); in spi_imx_sdma_exit()
1318 controller->dma_rx = NULL; in spi_imx_sdma_exit()
1321 if (controller->dma_tx) { in spi_imx_sdma_exit()
1322 dma_release_channel(controller->dma_tx); in spi_imx_sdma_exit()
1323 controller->dma_tx = NULL; in spi_imx_sdma_exit()
1332 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2; in spi_imx_sdma_init()
1334 /* Prepare for TX DMA: */ in spi_imx_sdma_init()
1335 controller->dma_tx = dma_request_chan(dev, "tx"); in spi_imx_sdma_init()
1336 if (IS_ERR(controller->dma_tx)) { in spi_imx_sdma_init()
1337 ret = PTR_ERR(controller->dma_tx); in spi_imx_sdma_init()
1338 dev_err_probe(dev, ret, "can't get the TX DMA channel!\n"); in spi_imx_sdma_init()
1339 controller->dma_tx = NULL; in spi_imx_sdma_init()
1344 controller->dma_rx = dma_request_chan(dev, "rx"); in spi_imx_sdma_init()
1345 if (IS_ERR(controller->dma_rx)) { in spi_imx_sdma_init()
1346 ret = PTR_ERR(controller->dma_rx); in spi_imx_sdma_init()
1348 controller->dma_rx = NULL; in spi_imx_sdma_init()
1352 init_completion(&spi_imx->dma_rx_completion); in spi_imx_sdma_init()
1353 init_completion(&spi_imx->dma_tx_completion); in spi_imx_sdma_init()
1354 controller->can_dma = spi_imx_can_dma; in spi_imx_sdma_init()
1355 controller->max_dma_len = MAX_SDMA_BD_BYTES; in spi_imx_sdma_init()
1356 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX | in spi_imx_sdma_init()
1369 complete(&spi_imx->dma_rx_completion); in spi_imx_dma_rx_callback()
1376 complete(&spi_imx->dma_tx_completion); in spi_imx_dma_tx_callback()
1384 timeout = (8 + 4) * size / spi_imx->spi_bus_clk; in spi_imx_calculate_timeout()
1399 struct spi_controller *controller = spi_imx->controller; in spi_imx_dma_transfer()
1400 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg; in spi_imx_dma_transfer() local
1401 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents); in spi_imx_dma_transfer()
1406 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word); in spi_imx_dma_transfer()
1407 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) { in spi_imx_dma_transfer()
1415 spi_imx->wml = i; in spi_imx_dma_transfer()
1421 if (!spi_imx->devtype_data->setup_wml) { in spi_imx_dma_transfer()
1422 dev_err(spi_imx->dev, "No setup_wml()?\n"); in spi_imx_dma_transfer()
1423 ret = -EINVAL; in spi_imx_dma_transfer()
1426 spi_imx->devtype_data->setup_wml(spi_imx); in spi_imx_dma_transfer()
1429 * The TX DMA setup starts the transfer, so make sure RX is configured in spi_imx_dma_transfer()
1430 * before TX. in spi_imx_dma_transfer()
1432 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx, in spi_imx_dma_transfer()
1433 rx->sgl, rx->nents, DMA_DEV_TO_MEM, in spi_imx_dma_transfer()
1436 ret = -EINVAL; in spi_imx_dma_transfer()
1440 desc_rx->callback = spi_imx_dma_rx_callback; in spi_imx_dma_transfer()
1441 desc_rx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1443 reinit_completion(&spi_imx->dma_rx_completion); in spi_imx_dma_transfer()
1444 dma_async_issue_pending(controller->dma_rx); in spi_imx_dma_transfer()
1446 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx, in spi_imx_dma_transfer()
1447 tx->sgl, tx->nents, DMA_MEM_TO_DEV, in spi_imx_dma_transfer()
1450 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1451 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1452 return -EINVAL; in spi_imx_dma_transfer()
1455 desc_tx->callback = spi_imx_dma_tx_callback; in spi_imx_dma_transfer()
1456 desc_tx->callback_param = (void *)spi_imx; in spi_imx_dma_transfer()
1458 reinit_completion(&spi_imx->dma_tx_completion); in spi_imx_dma_transfer()
1459 dma_async_issue_pending(controller->dma_tx); in spi_imx_dma_transfer()
1461 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_dma_transfer()
1464 time_left = wait_for_completion_timeout(&spi_imx->dma_tx_completion, in spi_imx_dma_transfer()
1467 dev_err(spi_imx->dev, "I/O Error in DMA TX\n"); in spi_imx_dma_transfer()
1468 dmaengine_terminate_all(controller->dma_tx); in spi_imx_dma_transfer()
1469 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1470 return -ETIMEDOUT; in spi_imx_dma_transfer()
1473 time_left = wait_for_completion_timeout(&spi_imx->dma_rx_completion, in spi_imx_dma_transfer()
1476 dev_err(&controller->dev, "I/O Error in DMA RX\n"); in spi_imx_dma_transfer()
1477 spi_imx->devtype_data->reset(spi_imx); in spi_imx_dma_transfer()
1478 dmaengine_terminate_all(controller->dma_rx); in spi_imx_dma_transfer()
1479 return -ETIMEDOUT; in spi_imx_dma_transfer()
1485 transfer->error |= SPI_TRANS_FAIL_NO_START; in spi_imx_dma_transfer()
1492 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer()
1496 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer()
1497 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer()
1498 spi_imx->count = transfer->len; in spi_imx_pio_transfer()
1499 spi_imx->txfifo = 0; in spi_imx_pio_transfer()
1500 spi_imx->remainder = 0; in spi_imx_pio_transfer()
1502 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer()
1506 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); in spi_imx_pio_transfer()
1508 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); in spi_imx_pio_transfer()
1510 time_left = wait_for_completion_timeout(&spi_imx->xfer_done, in spi_imx_pio_transfer()
1513 dev_err(&spi->dev, "I/O Error in PIO\n"); in spi_imx_pio_transfer()
1514 spi_imx->devtype_data->reset(spi_imx); in spi_imx_pio_transfer()
1515 return -ETIMEDOUT; in spi_imx_pio_transfer()
1524 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_poll_transfer()
1527 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_poll_transfer()
1528 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_poll_transfer()
1529 spi_imx->count = transfer->len; in spi_imx_poll_transfer()
1530 spi_imx->txfifo = 0; in spi_imx_poll_transfer()
1531 spi_imx->remainder = 0; in spi_imx_poll_transfer()
1539 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies; in spi_imx_poll_transfer()
1540 while (spi_imx->txfifo) { in spi_imx_poll_transfer()
1542 while (spi_imx->txfifo && in spi_imx_poll_transfer()
1543 spi_imx->devtype_data->rx_available(spi_imx)) { in spi_imx_poll_transfer()
1544 spi_imx->rx(spi_imx); in spi_imx_poll_transfer()
1545 spi_imx->txfifo--; in spi_imx_poll_transfer()
1548 /* TX */ in spi_imx_poll_transfer()
1549 if (spi_imx->count) { in spi_imx_poll_transfer()
1554 if (spi_imx->txfifo && in spi_imx_poll_transfer()
1557 dev_err_ratelimited(&spi->dev, in spi_imx_poll_transfer()
1558 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n", in spi_imx_poll_transfer()
1559 jiffies - timeout); in spi_imx_poll_transfer()
1572 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_pio_transfer_target()
1576 transfer->len > MX53_MAX_TRANSFER_BYTES) { in spi_imx_pio_transfer_target()
1577 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n", in spi_imx_pio_transfer_target()
1579 return -EMSGSIZE; in spi_imx_pio_transfer_target()
1582 spi_imx->tx_buf = transfer->tx_buf; in spi_imx_pio_transfer_target()
1583 spi_imx->rx_buf = transfer->rx_buf; in spi_imx_pio_transfer_target()
1584 spi_imx->count = transfer->len; in spi_imx_pio_transfer_target()
1585 spi_imx->txfifo = 0; in spi_imx_pio_transfer_target()
1586 spi_imx->remainder = 0; in spi_imx_pio_transfer_target()
1588 reinit_completion(&spi_imx->xfer_done); in spi_imx_pio_transfer_target()
1589 spi_imx->target_aborted = false; in spi_imx_pio_transfer_target()
1593 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR); in spi_imx_pio_transfer_target()
1595 if (wait_for_completion_interruptible(&spi_imx->xfer_done) || in spi_imx_pio_transfer_target()
1596 spi_imx->target_aborted) { in spi_imx_pio_transfer_target()
1597 dev_dbg(&spi->dev, "interrupted\n"); in spi_imx_pio_transfer_target()
1598 ret = -EINTR; in spi_imx_pio_transfer_target()
1607 if (spi_imx->devtype_data->disable) in spi_imx_pio_transfer_target()
1608 spi_imx->devtype_data->disable(spi_imx); in spi_imx_pio_transfer_target()
1617 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller); in spi_imx_transfer_one()
1621 transfer->effective_speed_hz = spi_imx->spi_bus_clk; in spi_imx_transfer_one()
1624 while (spi_imx->devtype_data->rx_available(spi_imx)) in spi_imx_transfer_one()
1625 readl(spi_imx->base + MXC_CSPIRXDATA); in spi_imx_transfer_one()
1627 if (spi_imx->target_mode) in spi_imx_transfer_one()
1635 if (spi_imx->usedma) in spi_imx_transfer_one()
1642 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1; in spi_imx_transfer_one()
1645 if (transfer->len < byte_limit) in spi_imx_transfer_one()
1653 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, in spi_imx_setup()
1654 spi->mode, spi->bits_per_word, spi->max_speed_hz); in spi_imx_setup()
1665 ret = pm_runtime_resume_and_get(spi_imx->dev); in spi_imx_prepare_message()
1667 dev_err(spi_imx->dev, "failed to enable clock\n"); in spi_imx_prepare_message()
1671 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg); in spi_imx_prepare_message()
1673 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_prepare_message()
1674 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_prepare_message()
1685 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_unprepare_message()
1686 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_unprepare_message()
1694 spi_imx->target_aborted = true; in spi_imx_target_abort()
1695 complete(&spi_imx->xfer_done); in spi_imx_target_abort()
1702 struct device_node *np = pdev->dev.of_node; in spi_imx_probe()
1708 of_device_get_match_data(&pdev->dev); in spi_imx_probe()
1712 target_mode = devtype_data->has_targetmode && in spi_imx_probe()
1713 of_property_read_bool(np, "spi-slave"); in spi_imx_probe()
1715 controller = spi_alloc_target(&pdev->dev, in spi_imx_probe()
1718 controller = spi_alloc_host(&pdev->dev, in spi_imx_probe()
1721 return -ENOMEM; in spi_imx_probe()
1723 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl); in spi_imx_probe()
1731 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); in spi_imx_probe()
1732 controller->bus_num = np ? -1 : pdev->id; in spi_imx_probe()
1733 controller->use_gpio_descriptors = true; in spi_imx_probe()
1736 spi_imx->controller = controller; in spi_imx_probe()
1737 spi_imx->dev = &pdev->dev; in spi_imx_probe()
1738 spi_imx->target_mode = target_mode; in spi_imx_probe()
1740 spi_imx->devtype_data = devtype_data; in spi_imx_probe()
1748 if (!device_property_read_u32(&pdev->dev, "num-cs", &val)) in spi_imx_probe()
1749 controller->num_chipselect = val; in spi_imx_probe()
1751 controller->num_chipselect = 3; in spi_imx_probe()
1753 controller->transfer_one = spi_imx_transfer_one; in spi_imx_probe()
1754 controller->setup = spi_imx_setup; in spi_imx_probe()
1755 controller->prepare_message = spi_imx_prepare_message; in spi_imx_probe()
1756 controller->unprepare_message = spi_imx_unprepare_message; in spi_imx_probe()
1757 controller->target_abort = spi_imx_target_abort; in spi_imx_probe()
1758 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS | in spi_imx_probe()
1763 controller->mode_bits |= SPI_LOOP | SPI_READY; in spi_imx_probe()
1766 controller->mode_bits |= SPI_RX_CPHA_FLIP; in spi_imx_probe()
1769 device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) in spi_imx_probe()
1771 * When using HW-CS implementing SPI_CS_WORD can be done by just in spi_imx_probe()
1775 controller->mode_bits |= SPI_CS_WORD; in spi_imx_probe()
1778 controller->max_native_cs = 4; in spi_imx_probe()
1779 controller->flags |= SPI_CONTROLLER_GPIO_SS; in spi_imx_probe()
1782 spi_imx->spi_drctl = spi_drctl; in spi_imx_probe()
1784 init_completion(&spi_imx->xfer_done); in spi_imx_probe()
1786 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in spi_imx_probe()
1787 if (IS_ERR(spi_imx->base)) { in spi_imx_probe()
1788 ret = PTR_ERR(spi_imx->base); in spi_imx_probe()
1791 spi_imx->base_phys = res->start; in spi_imx_probe()
1799 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0, in spi_imx_probe()
1800 dev_name(&pdev->dev), spi_imx); in spi_imx_probe()
1802 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret); in spi_imx_probe()
1806 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in spi_imx_probe()
1807 if (IS_ERR(spi_imx->clk_ipg)) { in spi_imx_probe()
1808 ret = PTR_ERR(spi_imx->clk_ipg); in spi_imx_probe()
1812 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per"); in spi_imx_probe()
1813 if (IS_ERR(spi_imx->clk_per)) { in spi_imx_probe()
1814 ret = PTR_ERR(spi_imx->clk_per); in spi_imx_probe()
1818 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_probe()
1822 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_probe()
1826 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT); in spi_imx_probe()
1827 pm_runtime_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1828 pm_runtime_get_noresume(spi_imx->dev); in spi_imx_probe()
1829 pm_runtime_set_active(spi_imx->dev); in spi_imx_probe()
1830 pm_runtime_enable(spi_imx->dev); in spi_imx_probe()
1832 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per); in spi_imx_probe()
1837 if (spi_imx->devtype_data->has_dmamode) { in spi_imx_probe()
1838 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller); in spi_imx_probe()
1839 if (ret == -EPROBE_DEFER) in spi_imx_probe()
1843 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n", in spi_imx_probe()
1847 spi_imx->devtype_data->reset(spi_imx); in spi_imx_probe()
1849 spi_imx->devtype_data->intctrl(spi_imx, 0); in spi_imx_probe()
1851 controller->dev.of_node = pdev->dev.of_node; in spi_imx_probe()
1854 dev_err_probe(&pdev->dev, ret, "register controller failed\n"); in spi_imx_probe()
1858 pm_runtime_mark_last_busy(spi_imx->dev); in spi_imx_probe()
1859 pm_runtime_put_autosuspend(spi_imx->dev); in spi_imx_probe()
1864 if (spi_imx->devtype_data->has_dmamode) in spi_imx_probe()
1867 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_probe()
1868 pm_runtime_disable(spi_imx->dev); in spi_imx_probe()
1869 pm_runtime_set_suspended(&pdev->dev); in spi_imx_probe()
1871 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_probe()
1873 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_probe()
1888 ret = pm_runtime_get_sync(spi_imx->dev); in spi_imx_remove()
1890 writel(0, spi_imx->base + MXC_CSPICTRL); in spi_imx_remove()
1892 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n"); in spi_imx_remove()
1894 pm_runtime_dont_use_autosuspend(spi_imx->dev); in spi_imx_remove()
1895 pm_runtime_put_sync(spi_imx->dev); in spi_imx_remove()
1896 pm_runtime_disable(spi_imx->dev); in spi_imx_remove()
1909 ret = clk_prepare_enable(spi_imx->clk_per); in spi_imx_runtime_resume()
1913 ret = clk_prepare_enable(spi_imx->clk_ipg); in spi_imx_runtime_resume()
1915 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_resume()
1929 clk_disable_unprepare(spi_imx->clk_per); in spi_imx_runtime_suspend()
1930 clk_disable_unprepare(spi_imx->clk_ipg); in spi_imx_runtime_suspend()