Lines Matching +full:spi +full:- +full:src +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 #include <linux/clk.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/dma/qcom-gpi-dma.h>
16 #include <linux/soc/qcom/geni-se.h>
17 #include <linux/spi/spi.h>
20 /* SPI SE specific registers and respective register fields */
59 /* M_CMD OP codes for SPI */
66 /* M_CMD params for SPI */
108 struct geni_se *se = &mas->se; in spi_slv_setup()
110 writel(SPI_SLAVE_EN, se->base + SE_SPI_SLAVE_EN); in spi_slv_setup()
111 writel(GENI_IO_MUX_0_EN, se->base + GENI_OUTPUT_CTRL); in spi_slv_setup()
112 writel(START_TRIGGER, se->base + SE_GENI_CFG_SEQ_START); in spi_slv_setup()
113 dev_dbg(mas->dev, "spi slave setup done\n"); in spi_slv_setup()
125 ret = geni_se_clk_freq_match(&mas->se, in get_spi_clk_cfg()
126 speed_hz * mas->oversampling, in get_spi_clk_cfg()
129 dev_err(mas->dev, "Failed(%d) to find src clk for %dHz\n", in get_spi_clk_cfg()
134 *clk_div = DIV_ROUND_UP(sclk_freq, mas->oversampling * speed_hz); in get_spi_clk_cfg()
135 actual_hz = sclk_freq / (mas->oversampling * *clk_div); in get_spi_clk_cfg()
137 dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, in get_spi_clk_cfg()
139 ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); in get_spi_clk_cfg()
141 dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); in get_spi_clk_cfg()
143 mas->cur_sclk_hz = sclk_freq; in get_spi_clk_cfg()
148 static void handle_se_timeout(struct spi_controller *spi, in handle_se_timeout() argument
151 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in handle_se_timeout()
153 struct geni_se *se = &mas->se; in handle_se_timeout()
156 spin_lock_irq(&mas->lock); in handle_se_timeout()
157 if (mas->cur_xfer_mode == GENI_SE_FIFO) in handle_se_timeout()
158 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in handle_se_timeout()
160 xfer = mas->cur_xfer; in handle_se_timeout()
161 mas->cur_xfer = NULL; in handle_se_timeout()
163 if (spi->target) { in handle_se_timeout()
165 * skip CMD Cancel sequnece since spi target in handle_se_timeout()
168 spin_unlock_irq(&mas->lock); in handle_se_timeout()
172 reinit_completion(&mas->cancel_done); in handle_se_timeout()
174 spin_unlock_irq(&mas->lock); in handle_se_timeout()
176 time_left = wait_for_completion_timeout(&mas->cancel_done, HZ); in handle_se_timeout()
180 spin_lock_irq(&mas->lock); in handle_se_timeout()
181 reinit_completion(&mas->abort_done); in handle_se_timeout()
183 spin_unlock_irq(&mas->lock); in handle_se_timeout()
185 time_left = wait_for_completion_timeout(&mas->abort_done, HZ); in handle_se_timeout()
187 dev_err(mas->dev, "Failed to cancel/abort m_cmd\n"); in handle_se_timeout()
190 * No need for a lock since SPI core has a lock and we never in handle_se_timeout()
193 mas->abort_failed = true; in handle_se_timeout()
197 if (mas->cur_xfer_mode == GENI_SE_DMA) { in handle_se_timeout()
199 if (xfer->tx_buf) { in handle_se_timeout()
200 spin_lock_irq(&mas->lock); in handle_se_timeout()
201 reinit_completion(&mas->tx_reset_done); in handle_se_timeout()
202 writel(1, se->base + SE_DMA_TX_FSM_RST); in handle_se_timeout()
203 spin_unlock_irq(&mas->lock); in handle_se_timeout()
204 time_left = wait_for_completion_timeout(&mas->tx_reset_done, HZ); in handle_se_timeout()
206 dev_err(mas->dev, "DMA TX RESET failed\n"); in handle_se_timeout()
208 if (xfer->rx_buf) { in handle_se_timeout()
209 spin_lock_irq(&mas->lock); in handle_se_timeout()
210 reinit_completion(&mas->rx_reset_done); in handle_se_timeout()
211 writel(1, se->base + SE_DMA_RX_FSM_RST); in handle_se_timeout()
212 spin_unlock_irq(&mas->lock); in handle_se_timeout()
213 time_left = wait_for_completion_timeout(&mas->rx_reset_done, HZ); in handle_se_timeout()
215 dev_err(mas->dev, "DMA RX RESET failed\n"); in handle_se_timeout()
223 dev_warn(mas->dev, "Cancel/Abort on completed SPI transfer\n"); in handle_se_timeout()
228 static void handle_gpi_timeout(struct spi_controller *spi, struct spi_message *msg) in handle_gpi_timeout() argument
230 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in handle_gpi_timeout()
232 dmaengine_terminate_sync(mas->tx); in handle_gpi_timeout()
233 dmaengine_terminate_sync(mas->rx); in handle_gpi_timeout()
236 static void spi_geni_handle_err(struct spi_controller *spi, struct spi_message *msg) in spi_geni_handle_err() argument
238 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in spi_geni_handle_err()
240 switch (mas->cur_xfer_mode) { in spi_geni_handle_err()
243 handle_se_timeout(spi, msg); in spi_geni_handle_err()
246 handle_gpi_timeout(spi, msg); in spi_geni_handle_err()
249 dev_err(mas->dev, "Abort on Mode:%d not supported", mas->cur_xfer_mode); in spi_geni_handle_err()
255 struct geni_se *se = &mas->se; in spi_geni_is_abort_still_pending()
258 if (!mas->abort_failed) in spi_geni_is_abort_still_pending()
267 spin_lock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
268 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in spi_geni_is_abort_still_pending()
269 m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); in spi_geni_is_abort_still_pending()
270 spin_unlock_irq(&mas->lock); in spi_geni_is_abort_still_pending()
273 dev_err(mas->dev, "Interrupts pending after abort: %#010x\n", in spi_geni_is_abort_still_pending()
282 mas->abort_failed = false; in spi_geni_is_abort_still_pending()
289 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller); in spi_geni_set_cs()
290 struct spi_controller *spi = dev_get_drvdata(mas->dev); in spi_geni_set_cs() local
291 struct geni_se *se = &mas->se; in spi_geni_set_cs()
294 if (!(slv->mode & SPI_CS_HIGH)) in spi_geni_set_cs()
297 if (set_flag == mas->cs_flag) in spi_geni_set_cs()
300 pm_runtime_get_sync(mas->dev); in spi_geni_set_cs()
303 dev_err(mas->dev, "Can't set chip select\n"); in spi_geni_set_cs()
307 spin_lock_irq(&mas->lock); in spi_geni_set_cs()
308 if (mas->cur_xfer) { in spi_geni_set_cs()
309 dev_err(mas->dev, "Can't set CS when prev xfer running\n"); in spi_geni_set_cs()
310 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
314 mas->cs_flag = set_flag; in spi_geni_set_cs()
316 mas->cur_xfer_mode = GENI_SE_FIFO; in spi_geni_set_cs()
317 geni_se_select_mode(se, mas->cur_xfer_mode); in spi_geni_set_cs()
319 reinit_completion(&mas->cs_done); in spi_geni_set_cs()
324 spin_unlock_irq(&mas->lock); in spi_geni_set_cs()
326 time_left = wait_for_completion_timeout(&mas->cs_done, HZ); in spi_geni_set_cs()
328 dev_warn(mas->dev, "Timeout setting chip select\n"); in spi_geni_set_cs()
329 handle_se_timeout(spi, NULL); in spi_geni_set_cs()
333 pm_runtime_put(mas->dev); in spi_geni_set_cs()
341 struct geni_se *se = &mas->se; in spi_setup_word_len()
346 * 1 SPI word per FIFO word. in spi_setup_word_len()
348 if (!(mas->fifo_width_bits % bits_per_word)) in spi_setup_word_len()
349 pack_words = mas->fifo_width_bits / bits_per_word; in spi_setup_word_len()
352 geni_se_config_packing(&mas->se, bits_per_word, pack_words, msb_first, in spi_setup_word_len()
354 word_len = (bits_per_word - MIN_WORD_LEN) & WORD_LEN_MSK; in spi_setup_word_len()
355 writel(word_len, se->base + SE_SPI_WORD_LEN); in spi_setup_word_len()
362 struct geni_se *se = &mas->se; in geni_spi_set_clock_and_bw()
365 if (clk_hz == mas->cur_speed_hz) in geni_spi_set_clock_and_bw()
370 dev_err(mas->dev, "Err setting clk to %lu: %d\n", clk_hz, ret); in geni_spi_set_clock_and_bw()
375 * SPI core clock gets configured with the requested frequency in geni_spi_set_clock_and_bw()
381 mas->cur_speed_hz = clk_hz; in geni_spi_set_clock_and_bw()
385 writel(clk_sel, se->base + SE_GENI_CLK_SEL); in geni_spi_set_clock_and_bw()
386 writel(m_clk_cfg, se->base + GENI_SER_M_CLK_CFG); in geni_spi_set_clock_and_bw()
389 se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz); in geni_spi_set_clock_and_bw()
398 struct spi_controller *spi) in setup_fifo_params() argument
400 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in setup_fifo_params()
401 struct geni_se *se = &mas->se; in setup_fifo_params()
405 if (mas->last_mode != spi_slv->mode) { in setup_fifo_params()
406 if (spi_slv->mode & SPI_LOOP) in setup_fifo_params()
409 if (spi_slv->mode & SPI_CPOL) in setup_fifo_params()
412 if (spi_slv->mode & SPI_CPHA) in setup_fifo_params()
415 if (spi_slv->mode & SPI_CS_HIGH) in setup_fifo_params()
419 mas->cur_bits_per_word = spi_slv->bits_per_word; in setup_fifo_params()
421 spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word); in setup_fifo_params()
422 writel(loopback_cfg, se->base + SE_SPI_LOOPBACK); in setup_fifo_params()
423 writel(demux_sel, se->base + SE_SPI_DEMUX_SEL); in setup_fifo_params()
424 writel(cpha, se->base + SE_SPI_CPHA); in setup_fifo_params()
425 writel(cpol, se->base + SE_SPI_CPOL); in setup_fifo_params()
426 writel(demux_output_inv, se->base + SE_SPI_DEMUX_OUTPUT_INV); in setup_fifo_params()
428 mas->last_mode = spi_slv->mode; in setup_fifo_params()
431 return geni_spi_set_clock_and_bw(mas, spi_slv->max_speed_hz); in setup_fifo_params()
437 struct spi_controller *spi = cb; in spi_gsi_callback_result() local
439 spi->cur_msg->status = -EIO; in spi_gsi_callback_result()
440 if (result->result != DMA_TRANS_NOERROR) { in spi_gsi_callback_result()
441 dev_err(&spi->dev, "DMA txn failed: %d\n", result->result); in spi_gsi_callback_result()
442 spi_finalize_current_transfer(spi); in spi_gsi_callback_result()
446 if (!result->residue) { in spi_gsi_callback_result()
447 spi->cur_msg->status = 0; in spi_gsi_callback_result()
448 dev_dbg(&spi->dev, "DMA txn completed\n"); in spi_gsi_callback_result()
450 dev_err(&spi->dev, "DMA xfer has pending: %d\n", result->residue); in spi_gsi_callback_result()
453 spi_finalize_current_transfer(spi); in spi_gsi_callback_result()
457 struct spi_device *spi_slv, struct spi_controller *spi) in setup_gsi_xfer() argument
469 if (xfer->bits_per_word != mas->cur_bits_per_word || in setup_gsi_xfer()
470 xfer->speed_hz != mas->cur_speed_hz) { in setup_gsi_xfer()
471 mas->cur_bits_per_word = xfer->bits_per_word; in setup_gsi_xfer()
472 mas->cur_speed_hz = xfer->speed_hz; in setup_gsi_xfer()
475 if (xfer->tx_buf && xfer->rx_buf) { in setup_gsi_xfer()
477 } else if (xfer->tx_buf) { in setup_gsi_xfer()
480 } else if (xfer->rx_buf) { in setup_gsi_xfer()
482 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) { in setup_gsi_xfer()
483 peripheral.rx_len = ((xfer->len << 3) / mas->cur_bits_per_word); in setup_gsi_xfer()
485 int bytes_per_word = (mas->cur_bits_per_word / BITS_PER_BYTE) + 1; in setup_gsi_xfer()
487 peripheral.rx_len = (xfer->len / bytes_per_word); in setup_gsi_xfer()
491 peripheral.loopback_en = !!(spi_slv->mode & SPI_LOOP); in setup_gsi_xfer()
492 peripheral.clock_pol_high = !!(spi_slv->mode & SPI_CPOL); in setup_gsi_xfer()
493 peripheral.data_pol_high = !!(spi_slv->mode & SPI_CPHA); in setup_gsi_xfer()
496 peripheral.word_len = xfer->bits_per_word - MIN_WORD_LEN; in setup_gsi_xfer()
498 ret = get_spi_clk_cfg(mas->cur_speed_hz, mas, in setup_gsi_xfer()
501 dev_err(mas->dev, "Err in get_spi_clk_cfg() :%d\n", ret); in setup_gsi_xfer()
505 if (!xfer->cs_change) { in setup_gsi_xfer()
506 if (!list_is_last(&xfer->transfer_list, &spi->cur_msg->transfers)) in setup_gsi_xfer()
511 dmaengine_slave_config(mas->rx, &config); in setup_gsi_xfer()
512 rx_desc = dmaengine_prep_slave_sg(mas->rx, xfer->rx_sg.sgl, xfer->rx_sg.nents, in setup_gsi_xfer()
515 dev_err(mas->dev, "Err setting up rx desc\n"); in setup_gsi_xfer()
516 return -EIO; in setup_gsi_xfer()
524 dmaengine_slave_config(mas->tx, &config); in setup_gsi_xfer()
525 tx_desc = dmaengine_prep_slave_sg(mas->tx, xfer->tx_sg.sgl, xfer->tx_sg.nents, in setup_gsi_xfer()
528 dev_err(mas->dev, "Err setting up tx desc\n"); in setup_gsi_xfer()
529 return -EIO; in setup_gsi_xfer()
532 tx_desc->callback_result = spi_gsi_callback_result; in setup_gsi_xfer()
533 tx_desc->callback_param = spi; in setup_gsi_xfer()
540 dma_async_issue_pending(mas->rx); in setup_gsi_xfer()
542 dma_async_issue_pending(mas->tx); in setup_gsi_xfer()
551 if (!(mas->cur_bits_per_word % MIN_WORD_LEN)) in get_xfer_len_in_words()
552 len = xfer->len * BITS_PER_BYTE / mas->cur_bits_per_word; in get_xfer_len_in_words()
554 len = xfer->len / (mas->cur_bits_per_word / BITS_PER_BYTE + 1); in get_xfer_len_in_words()
563 struct spi_geni_master *mas = spi_controller_get_devdata(slv->controller); in geni_can_dma()
566 if (mas->cur_xfer_mode == GENI_GPI_DMA) in geni_can_dma()
569 /* Set SE DMA mode for SPI target. */ in geni_can_dma()
570 if (ctlr->target) in geni_can_dma()
574 fifo_size = mas->tx_fifo_depth * mas->fifo_width_bits / mas->cur_bits_per_word; in geni_can_dma()
582 static int spi_geni_prepare_message(struct spi_controller *spi, in spi_geni_prepare_message() argument
585 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in spi_geni_prepare_message()
588 switch (mas->cur_xfer_mode) { in spi_geni_prepare_message()
592 return -EBUSY; in spi_geni_prepare_message()
593 ret = setup_fifo_params(spi_msg->spi, spi); in spi_geni_prepare_message()
595 dev_err(mas->dev, "Couldn't select mode %d\n", ret); in spi_geni_prepare_message()
603 dev_err(mas->dev, "Mode not supported %d", mas->cur_xfer_mode); in spi_geni_prepare_message()
604 return -EINVAL; in spi_geni_prepare_message()
611 if (mas->rx) { in spi_geni_release_dma_chan()
612 dma_release_channel(mas->rx); in spi_geni_release_dma_chan()
613 mas->rx = NULL; in spi_geni_release_dma_chan()
616 if (mas->tx) { in spi_geni_release_dma_chan()
617 dma_release_channel(mas->tx); in spi_geni_release_dma_chan()
618 mas->tx = NULL; in spi_geni_release_dma_chan()
626 mas->tx = dma_request_chan(mas->dev, "tx"); in spi_geni_grab_gpi_chan()
627 if (IS_ERR(mas->tx)) { in spi_geni_grab_gpi_chan()
628 ret = dev_err_probe(mas->dev, PTR_ERR(mas->tx), in spi_geni_grab_gpi_chan()
633 mas->rx = dma_request_chan(mas->dev, "rx"); in spi_geni_grab_gpi_chan()
634 if (IS_ERR(mas->rx)) { in spi_geni_grab_gpi_chan()
635 ret = dev_err_probe(mas->dev, PTR_ERR(mas->rx), in spi_geni_grab_gpi_chan()
640 ret = devm_add_action_or_reset(mas->dev, spi_geni_release_dma_chan, mas); in spi_geni_grab_gpi_chan()
642 dev_err(mas->dev, "Unable to add action.\n"); in spi_geni_grab_gpi_chan()
649 mas->rx = NULL; in spi_geni_grab_gpi_chan()
650 dma_release_channel(mas->tx); in spi_geni_grab_gpi_chan()
652 mas->tx = NULL; in spi_geni_grab_gpi_chan()
658 struct spi_controller *spi = dev_get_drvdata(mas->dev); in spi_geni_init() local
659 struct geni_se *se = &mas->se; in spi_geni_init()
662 int ret = -ENXIO; in spi_geni_init()
664 pm_runtime_get_sync(mas->dev); in spi_geni_init()
668 if (spi->target) { in spi_geni_init()
670 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
675 dev_err(mas->dev, "Invalid proto %d\n", proto); in spi_geni_init()
678 mas->tx_fifo_depth = geni_se_get_tx_fifo_depth(se); in spi_geni_init()
681 mas->fifo_width_bits = geni_se_get_tx_fifo_width(se); in spi_geni_init()
685 * RX FIFO RFR level to fifo_depth-2. in spi_geni_init()
687 geni_se_init(se, mas->tx_fifo_depth - 3, mas->tx_fifo_depth - 2); in spi_geni_init()
689 mas->tx_wm = 1; in spi_geni_init()
695 mas->oversampling = 2; in spi_geni_init()
697 mas->oversampling = 1; in spi_geni_init()
699 fifo_disable = readl(se->base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE; in spi_geni_init()
704 mas->cur_xfer_mode = GENI_GPI_DMA; in spi_geni_init()
706 dev_dbg(mas->dev, "Using GPI DMA mode for SPI\n"); in spi_geni_init()
708 } else if (ret == -EPROBE_DEFER) { in spi_geni_init()
715 dev_warn(mas->dev, "FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode\n"); in spi_geni_init()
719 mas->cur_xfer_mode = GENI_SE_FIFO; in spi_geni_init()
726 if (!spi->target) { in spi_geni_init()
727 spi_tx_cfg = readl(se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
729 writel(spi_tx_cfg, se->base + SE_SPI_TRANS_CFG); in spi_geni_init()
733 pm_runtime_put(mas->dev); in spi_geni_init()
744 if (mas->fifo_width_bits % mas->cur_bits_per_word) in geni_byte_per_fifo_word()
745 return roundup_pow_of_two(DIV_ROUND_UP(mas->cur_bits_per_word, in geni_byte_per_fifo_word()
748 return mas->fifo_width_bits / BITS_PER_BYTE; in geni_byte_per_fifo_word()
753 struct geni_se *se = &mas->se; in geni_spi_handle_tx()
760 if (!mas->cur_xfer) { in geni_spi_handle_tx()
761 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
765 max_bytes = (mas->tx_fifo_depth - mas->tx_wm) * bytes_per_fifo_word; in geni_spi_handle_tx()
766 if (mas->tx_rem_bytes < max_bytes) in geni_spi_handle_tx()
767 max_bytes = mas->tx_rem_bytes; in geni_spi_handle_tx()
769 tx_buf = mas->cur_xfer->tx_buf + mas->cur_xfer->len - mas->tx_rem_bytes; in geni_spi_handle_tx()
776 bytes_to_write = min(bytes_per_fifo_word, max_bytes - i); in geni_spi_handle_tx()
779 iowrite32_rep(se->base + SE_GENI_TX_FIFOn, &fifo_word, 1); in geni_spi_handle_tx()
781 mas->tx_rem_bytes -= max_bytes; in geni_spi_handle_tx()
782 if (!mas->tx_rem_bytes) { in geni_spi_handle_tx()
783 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_handle_tx()
791 struct geni_se *se = &mas->se; in geni_spi_handle_rx()
799 rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); in geni_spi_handle_rx()
805 rx_bytes -= bytes_per_fifo_word - rx_last_byte_valid; in geni_spi_handle_rx()
809 if (!mas->cur_xfer) { in geni_spi_handle_rx()
811 readl(se->base + SE_GENI_RX_FIFOn); in geni_spi_handle_rx()
815 if (mas->rx_rem_bytes < rx_bytes) in geni_spi_handle_rx()
816 rx_bytes = mas->rx_rem_bytes; in geni_spi_handle_rx()
818 rx_buf = mas->cur_xfer->rx_buf + mas->cur_xfer->len - mas->rx_rem_bytes; in geni_spi_handle_rx()
825 bytes_to_read = min(bytes_per_fifo_word, rx_bytes - i); in geni_spi_handle_rx()
826 ioread32_rep(se->base + SE_GENI_RX_FIFOn, &fifo_word, 1); in geni_spi_handle_rx()
830 mas->rx_rem_bytes -= rx_bytes; in geni_spi_handle_rx()
835 u16 mode, struct spi_controller *spi) in setup_se_xfer() argument
839 struct geni_se *se = &mas->se; in setup_se_xfer()
846 * worried about racing with out interrupt handler. The SPI core in setup_se_xfer()
854 spin_lock_irq(&mas->lock); in setup_se_xfer()
855 spin_unlock_irq(&mas->lock); in setup_se_xfer()
857 if (xfer->bits_per_word != mas->cur_bits_per_word) { in setup_se_xfer()
858 spi_setup_word_len(mas, mode, xfer->bits_per_word); in setup_se_xfer()
859 mas->cur_bits_per_word = xfer->bits_per_word; in setup_se_xfer()
863 ret = geni_spi_set_clock_and_bw(mas, xfer->speed_hz); in setup_se_xfer()
867 mas->tx_rem_bytes = 0; in setup_se_xfer()
868 mas->rx_rem_bytes = 0; in setup_se_xfer()
872 mas->cur_xfer = xfer; in setup_se_xfer()
873 if (xfer->tx_buf) { in setup_se_xfer()
875 mas->tx_rem_bytes = xfer->len; in setup_se_xfer()
876 writel(len, se->base + SE_SPI_TX_TRANS_LEN); in setup_se_xfer()
879 if (xfer->rx_buf) { in setup_se_xfer()
881 writel(len, se->base + SE_SPI_RX_TRANS_LEN); in setup_se_xfer()
882 mas->rx_rem_bytes = xfer->len; in setup_se_xfer()
891 if (!xfer->tx_sg.nents && !xfer->rx_sg.nents) in setup_se_xfer()
892 mas->cur_xfer_mode = GENI_SE_FIFO; in setup_se_xfer()
893 else if (xfer->tx_sg.nents > 1 || xfer->rx_sg.nents > 1) { in setup_se_xfer()
894 dev_warn_once(mas->dev, "Doing FIFO, cannot handle tx_nents-%d, rx_nents-%d\n", in setup_se_xfer()
895 xfer->tx_sg.nents, xfer->rx_sg.nents); in setup_se_xfer()
896 mas->cur_xfer_mode = GENI_SE_FIFO; in setup_se_xfer()
898 mas->cur_xfer_mode = GENI_SE_DMA; in setup_se_xfer()
899 geni_se_select_mode(se, mas->cur_xfer_mode); in setup_se_xfer()
905 spin_lock_irq(&mas->lock); in setup_se_xfer()
908 if (mas->cur_xfer_mode == GENI_SE_DMA) { in setup_se_xfer()
910 geni_se_rx_init_dma(se, sg_dma_address(xfer->rx_sg.sgl), in setup_se_xfer()
911 sg_dma_len(xfer->rx_sg.sgl)); in setup_se_xfer()
913 geni_se_tx_init_dma(se, sg_dma_address(xfer->tx_sg.sgl), in setup_se_xfer()
914 sg_dma_len(xfer->tx_sg.sgl)); in setup_se_xfer()
917 writel(mas->tx_wm, se->base + SE_GENI_TX_WATERMARK_REG); in setup_se_xfer()
920 spin_unlock_irq(&mas->lock); in setup_se_xfer()
924 static int spi_geni_transfer_one(struct spi_controller *spi, in spi_geni_transfer_one() argument
928 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in spi_geni_transfer_one()
932 return -EBUSY; in spi_geni_transfer_one()
935 if (!xfer->len) in spi_geni_transfer_one()
938 if (mas->cur_xfer_mode == GENI_SE_FIFO || mas->cur_xfer_mode == GENI_SE_DMA) { in spi_geni_transfer_one()
939 ret = setup_se_xfer(xfer, mas, slv->mode, spi); in spi_geni_transfer_one()
940 /* SPI framework expects +ve ret code to wait for transfer complete */ in spi_geni_transfer_one()
945 return setup_gsi_xfer(xfer, mas, slv, spi); in spi_geni_transfer_one()
950 struct spi_controller *spi = data; in geni_spi_isr() local
951 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in geni_spi_isr()
952 struct geni_se *se = &mas->se; in geni_spi_isr()
955 m_irq = readl(se->base + SE_GENI_M_IRQ_STATUS); in geni_spi_isr()
962 dev_warn(mas->dev, "Unexpected IRQ err status %#010x\n", m_irq); in geni_spi_isr()
964 spin_lock(&mas->lock); in geni_spi_isr()
966 if (mas->cur_xfer_mode == GENI_SE_FIFO) { in geni_spi_isr()
974 if (mas->cur_xfer) { in geni_spi_isr()
975 spi_finalize_current_transfer(spi); in geni_spi_isr()
976 mas->cur_xfer = NULL; in geni_spi_isr()
990 if (mas->tx_rem_bytes) { in geni_spi_isr()
991 writel(0, se->base + SE_GENI_TX_WATERMARK_REG); in geni_spi_isr()
992 dev_err(mas->dev, "Premature done. tx_rem = %d bpw%d\n", in geni_spi_isr()
993 mas->tx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
995 if (mas->rx_rem_bytes) in geni_spi_isr()
996 dev_err(mas->dev, "Premature done. rx_rem = %d bpw%d\n", in geni_spi_isr()
997 mas->rx_rem_bytes, mas->cur_bits_per_word); in geni_spi_isr()
999 complete(&mas->cs_done); in geni_spi_isr()
1002 } else if (mas->cur_xfer_mode == GENI_SE_DMA) { in geni_spi_isr()
1003 const struct spi_transfer *xfer = mas->cur_xfer; in geni_spi_isr()
1004 u32 dma_tx_status = readl_relaxed(se->base + SE_DMA_TX_IRQ_STAT); in geni_spi_isr()
1005 u32 dma_rx_status = readl_relaxed(se->base + SE_DMA_RX_IRQ_STAT); in geni_spi_isr()
1008 writel(dma_tx_status, se->base + SE_DMA_TX_IRQ_CLR); in geni_spi_isr()
1010 writel(dma_rx_status, se->base + SE_DMA_RX_IRQ_CLR); in geni_spi_isr()
1012 mas->tx_rem_bytes = 0; in geni_spi_isr()
1014 mas->rx_rem_bytes = 0; in geni_spi_isr()
1016 complete(&mas->tx_reset_done); in geni_spi_isr()
1018 complete(&mas->rx_reset_done); in geni_spi_isr()
1019 if (!mas->tx_rem_bytes && !mas->rx_rem_bytes && xfer) { in geni_spi_isr()
1020 spi_finalize_current_transfer(spi); in geni_spi_isr()
1021 mas->cur_xfer = NULL; in geni_spi_isr()
1026 complete(&mas->cancel_done); in geni_spi_isr()
1028 complete(&mas->abort_done); in geni_spi_isr()
1033 * - M_CMD_DONE_EN / M_RX_FIFO_LAST_EN: Edge triggered interrupts and in geni_spi_isr()
1038 * - M_RX_FIFO_WATERMARK_EN / M_TX_FIFO_WATERMARK_EN: These appear in geni_spi_isr()
1041 * since they'll re-assert if they're still happening. in geni_spi_isr()
1043 writel(m_irq, se->base + SE_GENI_M_IRQ_CLEAR); in geni_spi_isr()
1045 spin_unlock(&mas->lock); in geni_spi_isr()
1053 struct spi_controller *spi; in spi_geni_probe() local
1056 struct clk *clk; in spi_geni_probe() local
1057 struct device *dev = &pdev->dev; in spi_geni_probe()
1071 clk = devm_clk_get(dev, "se"); in spi_geni_probe()
1072 if (IS_ERR(clk)) in spi_geni_probe()
1073 return PTR_ERR(clk); in spi_geni_probe()
1075 spi = devm_spi_alloc_host(dev, sizeof(*mas)); in spi_geni_probe()
1076 if (!spi) in spi_geni_probe()
1077 return -ENOMEM; in spi_geni_probe()
1079 platform_set_drvdata(pdev, spi); in spi_geni_probe()
1080 mas = spi_controller_get_devdata(spi); in spi_geni_probe()
1081 mas->irq = irq; in spi_geni_probe()
1082 mas->dev = dev; in spi_geni_probe()
1083 mas->se.dev = dev; in spi_geni_probe()
1084 mas->se.wrapper = dev_get_drvdata(dev->parent); in spi_geni_probe()
1085 mas->se.base = base; in spi_geni_probe()
1086 mas->se.clk = clk; in spi_geni_probe()
1088 ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); in spi_geni_probe()
1092 ret = devm_pm_opp_of_add_table(&pdev->dev); in spi_geni_probe()
1093 if (ret && ret != -ENODEV) { in spi_geni_probe()
1094 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); in spi_geni_probe()
1098 spi->bus_num = -1; in spi_geni_probe()
1099 spi->dev.of_node = dev->of_node; in spi_geni_probe()
1100 spi->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH; in spi_geni_probe()
1101 spi->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); in spi_geni_probe()
1102 spi->num_chipselect = 4; in spi_geni_probe()
1103 spi->max_speed_hz = 50000000; in spi_geni_probe()
1104 spi->max_dma_len = 0xffff0; /* 24 bits for tx/rx dma length */ in spi_geni_probe()
1105 spi->prepare_message = spi_geni_prepare_message; in spi_geni_probe()
1106 spi->transfer_one = spi_geni_transfer_one; in spi_geni_probe()
1107 spi->can_dma = geni_can_dma; in spi_geni_probe()
1108 spi->dma_map_dev = dev->parent; in spi_geni_probe()
1109 spi->auto_runtime_pm = true; in spi_geni_probe()
1110 spi->handle_err = spi_geni_handle_err; in spi_geni_probe()
1111 spi->use_gpio_descriptors = true; in spi_geni_probe()
1113 init_completion(&mas->cs_done); in spi_geni_probe()
1114 init_completion(&mas->cancel_done); in spi_geni_probe()
1115 init_completion(&mas->abort_done); in spi_geni_probe()
1116 init_completion(&mas->tx_reset_done); in spi_geni_probe()
1117 init_completion(&mas->rx_reset_done); in spi_geni_probe()
1118 spin_lock_init(&mas->lock); in spi_geni_probe()
1120 ret = geni_icc_get(&mas->se, NULL); in spi_geni_probe()
1124 pm_runtime_use_autosuspend(&pdev->dev); in spi_geni_probe()
1125 pm_runtime_set_autosuspend_delay(&pdev->dev, 250); in spi_geni_probe()
1130 if (device_property_read_bool(&pdev->dev, "spi-slave")) in spi_geni_probe()
1131 spi->target = true; in spi_geni_probe()
1134 mas->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(CORE_2X_50_MHZ); in spi_geni_probe()
1135 mas->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; in spi_geni_probe()
1137 ret = geni_icc_set_bw(&mas->se); in spi_geni_probe()
1150 if (!spi->target && mas->cur_xfer_mode == GENI_SE_FIFO) in spi_geni_probe()
1151 spi->set_cs = spi_geni_set_cs; in spi_geni_probe()
1156 if (mas->cur_xfer_mode == GENI_GPI_DMA) in spi_geni_probe()
1157 spi->flags = SPI_CONTROLLER_MUST_TX; in spi_geni_probe()
1159 ret = devm_request_irq(dev, mas->irq, geni_spi_isr, 0, dev_name(dev), spi); in spi_geni_probe()
1163 return devm_spi_register_controller(dev, spi); in spi_geni_probe()
1168 struct spi_controller *spi = dev_get_drvdata(dev); in spi_geni_runtime_suspend() local
1169 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in spi_geni_runtime_suspend()
1175 ret = geni_se_resources_off(&mas->se); in spi_geni_runtime_suspend()
1179 return geni_icc_disable(&mas->se); in spi_geni_runtime_suspend()
1184 struct spi_controller *spi = dev_get_drvdata(dev); in spi_geni_runtime_resume() local
1185 struct spi_geni_master *mas = spi_controller_get_devdata(spi); in spi_geni_runtime_resume()
1188 ret = geni_icc_enable(&mas->se); in spi_geni_runtime_resume()
1192 ret = geni_se_resources_on(&mas->se); in spi_geni_runtime_resume()
1196 return dev_pm_opp_set_rate(mas->dev, mas->cur_sclk_hz); in spi_geni_runtime_resume()
1201 struct spi_controller *spi = dev_get_drvdata(dev); in spi_geni_suspend() local
1204 ret = spi_controller_suspend(spi); in spi_geni_suspend()
1210 spi_controller_resume(spi); in spi_geni_suspend()
1217 struct spi_controller *spi = dev_get_drvdata(dev); in spi_geni_resume() local
1224 ret = spi_controller_resume(spi); in spi_geni_resume()
1238 { .compatible = "qcom,geni-spi" },
1253 MODULE_DESCRIPTION("SPI driver for GENI based QUP cores");