Lines Matching +full:rx +full:- +full:input +full:- +full:m
1 // SPDX-License-Identifier: GPL-2.0-or-later
64 #define SPIE_RXT BIT(13) /* RX FIFO threshold */
65 #define SPIE_RXF BIT(12) /* RX FIFO full */
67 #define SPIE_RNE BIT(9) /* RX FIFO not empty */
73 #define SPIM_RXT BIT(13) /* RX FIFO threshold */
74 #define SPIM_RXF BIT(12) /* RX FIFO full */
76 #define SPIM_RNE BIT(9) /* RX FIFO not empty */
107 u32 spibrg; /* SPIBRG input clock */
118 return ioread32be(espi->reg_base + offset); in fsl_espi_read_reg()
123 return ioread16be(espi->reg_base + offset); in fsl_espi_read_reg16()
128 return ioread8(espi->reg_base + offset); in fsl_espi_read_reg8()
134 iowrite32be(val, espi->reg_base + offset); in fsl_espi_write_reg()
140 iowrite16be(val, espi->reg_base + offset); in fsl_espi_write_reg16()
146 iowrite8(val, espi->reg_base + offset); in fsl_espi_write_reg8()
149 static int fsl_espi_check_message(struct spi_message *m) in fsl_espi_check_message() argument
151 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_check_message()
154 if (m->frame_length > SPCOM_TRANLEN_MAX) { in fsl_espi_check_message()
155 dev_err(espi->dev, "message too long, size is %u bytes\n", in fsl_espi_check_message()
156 m->frame_length); in fsl_espi_check_message()
157 return -EMSGSIZE; in fsl_espi_check_message()
160 first = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_check_message()
163 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_check_message()
164 if (first->bits_per_word != t->bits_per_word || in fsl_espi_check_message()
165 first->speed_hz != t->speed_hz) { in fsl_espi_check_message()
166 dev_err(espi->dev, "bits_per_word/speed_hz should be the same for all transfers\n"); in fsl_espi_check_message()
167 return -EINVAL; in fsl_espi_check_message()
171 /* ESPI supports MSB-first transfers for word size 8 / 16 only */ in fsl_espi_check_message()
172 if (!(m->spi->mode & SPI_LSB_FIRST) && first->bits_per_word != 8 && in fsl_espi_check_message()
173 first->bits_per_word != 16) { in fsl_espi_check_message()
174 dev_err(espi->dev, in fsl_espi_check_message()
175 "MSB-first transfer not supported for wordsize %u\n", in fsl_espi_check_message()
176 first->bits_per_word); in fsl_espi_check_message()
177 return -EINVAL; in fsl_espi_check_message()
183 static unsigned int fsl_espi_check_rxskip_mode(struct spi_message *m) in fsl_espi_check_rxskip_mode() argument
190 * - message has two transfers in fsl_espi_check_rxskip_mode()
191 * - first transfer is a write and second is a read in fsl_espi_check_rxskip_mode()
193 * In addition the current low-level transfer mechanism requires in fsl_espi_check_rxskip_mode()
196 * the TX FIFO isn't re-filled. in fsl_espi_check_rxskip_mode()
198 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_check_rxskip_mode()
200 if (!t->tx_buf || t->rx_buf || in fsl_espi_check_rxskip_mode()
201 t->len > FSL_ESPI_FIFO_SIZE) in fsl_espi_check_rxskip_mode()
203 rxskip = t->len; in fsl_espi_check_rxskip_mode()
205 if (t->tx_buf || !t->rx_buf) in fsl_espi_check_rxskip_mode()
223 tx_left = espi->tx_t->len - espi->tx_pos; in fsl_espi_fill_tx_fifo()
224 tx_buf = espi->tx_t->tx_buf; in fsl_espi_fill_tx_fifo()
229 else if (espi->swab) in fsl_espi_fill_tx_fifo()
231 swahb32p(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
234 *(u32 *)(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
235 espi->tx_pos += 4; in fsl_espi_fill_tx_fifo()
236 tx_left -= 4; in fsl_espi_fill_tx_fifo()
237 tx_fifo_avail -= 4; in fsl_espi_fill_tx_fifo()
238 } else if (tx_left >= 2 && tx_buf && espi->swab) { in fsl_espi_fill_tx_fifo()
240 swab16p(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
241 espi->tx_pos += 2; in fsl_espi_fill_tx_fifo()
242 tx_left -= 2; in fsl_espi_fill_tx_fifo()
243 tx_fifo_avail -= 2; in fsl_espi_fill_tx_fifo()
249 *(u8 *)(tx_buf + espi->tx_pos)); in fsl_espi_fill_tx_fifo()
250 espi->tx_pos += 1; in fsl_espi_fill_tx_fifo()
251 tx_left -= 1; in fsl_espi_fill_tx_fifo()
252 tx_fifo_avail -= 1; in fsl_espi_fill_tx_fifo()
258 if (list_is_last(&espi->tx_t->transfer_list, in fsl_espi_fill_tx_fifo()
259 espi->m_transfers) || espi->rxskip) { in fsl_espi_fill_tx_fifo()
260 espi->tx_done = true; in fsl_espi_fill_tx_fifo()
263 espi->tx_t = list_next_entry(espi->tx_t, transfer_list); in fsl_espi_fill_tx_fifo()
264 espi->tx_pos = 0; in fsl_espi_fill_tx_fifo()
278 rx_left = espi->rx_t->len - espi->rx_pos; in fsl_espi_read_rx_fifo()
279 rx_buf = espi->rx_t->rx_buf; in fsl_espi_read_rx_fifo()
284 if (rx_buf && espi->swab) in fsl_espi_read_rx_fifo()
285 *(u32 *)(rx_buf + espi->rx_pos) = swahb32(val); in fsl_espi_read_rx_fifo()
287 *(u32 *)(rx_buf + espi->rx_pos) = val; in fsl_espi_read_rx_fifo()
288 espi->rx_pos += 4; in fsl_espi_read_rx_fifo()
289 rx_left -= 4; in fsl_espi_read_rx_fifo()
290 rx_fifo_avail -= 4; in fsl_espi_read_rx_fifo()
291 } else if (rx_left >= 2 && rx_buf && espi->swab) { in fsl_espi_read_rx_fifo()
294 *(u16 *)(rx_buf + espi->rx_pos) = swab16(val); in fsl_espi_read_rx_fifo()
295 espi->rx_pos += 2; in fsl_espi_read_rx_fifo()
296 rx_left -= 2; in fsl_espi_read_rx_fifo()
297 rx_fifo_avail -= 2; in fsl_espi_read_rx_fifo()
302 *(u8 *)(rx_buf + espi->rx_pos) = val; in fsl_espi_read_rx_fifo()
303 espi->rx_pos += 1; in fsl_espi_read_rx_fifo()
304 rx_left -= 1; in fsl_espi_read_rx_fifo()
305 rx_fifo_avail -= 1; in fsl_espi_read_rx_fifo()
310 if (list_is_last(&espi->rx_t->transfer_list, in fsl_espi_read_rx_fifo()
311 espi->m_transfers)) { in fsl_espi_read_rx_fifo()
312 espi->rx_done = true; in fsl_espi_read_rx_fifo()
315 espi->rx_t = list_next_entry(espi->rx_t, transfer_list); in fsl_espi_read_rx_fifo()
316 espi->rx_pos = 0; in fsl_espi_read_rx_fifo()
317 /* continue with next transfer if rx fifo is not empty */ in fsl_espi_read_rx_fifo()
326 struct fsl_espi *espi = spi_controller_get_devdata(spi->controller); in fsl_espi_setup_transfer()
327 int bits_per_word = t ? t->bits_per_word : spi->bits_per_word; in fsl_espi_setup_transfer()
328 u32 pm, hz = t ? t->speed_hz : spi->max_speed_hz; in fsl_espi_setup_transfer()
330 u32 hw_mode_old = cs->hw_mode; in fsl_espi_setup_transfer()
333 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF)); in fsl_espi_setup_transfer()
335 cs->hw_mode |= CSMODE_LEN(bits_per_word - 1); in fsl_espi_setup_transfer()
337 pm = DIV_ROUND_UP(espi->spibrg, hz * 4) - 1; in fsl_espi_setup_transfer()
340 cs->hw_mode |= CSMODE_DIV16; in fsl_espi_setup_transfer()
341 pm = DIV_ROUND_UP(espi->spibrg, hz * 16 * 4) - 1; in fsl_espi_setup_transfer()
344 cs->hw_mode |= CSMODE_PM(pm); in fsl_espi_setup_transfer()
347 if (cs->hw_mode != hw_mode_old) in fsl_espi_setup_transfer()
349 cs->hw_mode); in fsl_espi_setup_transfer()
354 struct fsl_espi *espi = spi_controller_get_devdata(spi->controller); in fsl_espi_bufs()
355 unsigned int rx_len = t->len; in fsl_espi_bufs()
359 reinit_completion(&espi->done); in fsl_espi_bufs()
363 spcom |= SPCOM_TRANLEN(t->len - 1); in fsl_espi_bufs()
366 if (espi->rxskip) { in fsl_espi_bufs()
367 spcom |= SPCOM_RXSKIP(espi->rxskip); in fsl_espi_bufs()
368 rx_len = t->len - espi->rxskip; in fsl_espi_bufs()
369 if (t->rx_nbits == SPI_NBITS_DUAL) in fsl_espi_bufs()
382 spin_lock_irq(&espi->lock); in fsl_espi_bufs()
384 spin_unlock_irq(&espi->lock); in fsl_espi_bufs()
387 ret = wait_for_completion_timeout(&espi->done, 2 * HZ); in fsl_espi_bufs()
389 dev_err(espi->dev, "Transfer timed out!\n"); in fsl_espi_bufs()
391 /* disable rx ints */ in fsl_espi_bufs()
394 return ret == 0 ? -ETIMEDOUT : 0; in fsl_espi_bufs()
397 static int fsl_espi_trans(struct spi_message *m, struct spi_transfer *trans) in fsl_espi_trans() argument
399 struct fsl_espi *espi = spi_controller_get_devdata(m->spi->controller); in fsl_espi_trans()
400 struct spi_device *spi = m->spi; in fsl_espi_trans()
403 /* In case of LSB-first and bits_per_word > 8 byte-swap all words */ in fsl_espi_trans()
404 espi->swab = spi->mode & SPI_LSB_FIRST && trans->bits_per_word > 8; in fsl_espi_trans()
406 espi->m_transfers = &m->transfers; in fsl_espi_trans()
407 espi->tx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
409 espi->tx_pos = 0; in fsl_espi_trans()
410 espi->tx_done = false; in fsl_espi_trans()
411 espi->rx_t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_trans()
413 espi->rx_pos = 0; in fsl_espi_trans()
414 espi->rx_done = false; in fsl_espi_trans()
416 espi->rxskip = fsl_espi_check_rxskip_mode(m); in fsl_espi_trans()
417 if (trans->rx_nbits == SPI_NBITS_DUAL && !espi->rxskip) { in fsl_espi_trans()
418 dev_err(espi->dev, "Dual output mode requires RXSKIP mode!\n"); in fsl_espi_trans()
419 return -EINVAL; in fsl_espi_trans()
423 if (espi->rxskip) in fsl_espi_trans()
424 espi->rx_t = list_next_entry(espi->rx_t, transfer_list); in fsl_espi_trans()
436 struct spi_message *m) in fsl_espi_do_one_msg() argument
442 ret = fsl_espi_check_message(m); in fsl_espi_do_one_msg()
446 list_for_each_entry(t, &m->transfers, transfer_list) { in fsl_espi_do_one_msg()
447 unsigned int delay = spi_delay_to_ns(&t->delay, t); in fsl_espi_do_one_msg()
451 if (t->rx_nbits > rx_nbits) in fsl_espi_do_one_msg()
452 rx_nbits = t->rx_nbits; in fsl_espi_do_one_msg()
455 t = list_first_entry(&m->transfers, struct spi_transfer, in fsl_espi_do_one_msg()
458 trans.len = m->frame_length; in fsl_espi_do_one_msg()
459 trans.speed_hz = t->speed_hz; in fsl_espi_do_one_msg()
460 trans.bits_per_word = t->bits_per_word; in fsl_espi_do_one_msg()
466 ret = fsl_espi_trans(m, &trans); in fsl_espi_do_one_msg()
468 m->actual_length = ret ? 0 : trans.len; in fsl_espi_do_one_msg()
470 if (m->status == -EINPROGRESS) in fsl_espi_do_one_msg()
471 m->status = ret; in fsl_espi_do_one_msg()
487 return -ENOMEM; in fsl_espi_setup()
491 espi = spi_controller_get_devdata(spi->controller); in fsl_espi_setup()
493 pm_runtime_get_sync(espi->dev); in fsl_espi_setup()
495 cs->hw_mode = fsl_espi_read_reg(espi, ESPI_SPMODEx(spi_get_chipselect(spi, 0))); in fsl_espi_setup()
497 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH in fsl_espi_setup()
500 if (spi->mode & SPI_CPHA) in fsl_espi_setup()
501 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK; in fsl_espi_setup()
502 if (spi->mode & SPI_CPOL) in fsl_espi_setup()
503 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH; in fsl_espi_setup()
504 if (!(spi->mode & SPI_LSB_FIRST)) in fsl_espi_setup()
505 cs->hw_mode |= CSMODE_REV; in fsl_espi_setup()
510 if (spi->mode & SPI_LOOP) in fsl_espi_setup()
516 pm_runtime_mark_last_busy(espi->dev); in fsl_espi_setup()
517 pm_runtime_put_autosuspend(espi->dev); in fsl_espi_setup()
532 if (!espi->rx_done) in fsl_espi_cpu_irq()
535 if (!espi->tx_done) in fsl_espi_cpu_irq()
538 if (!espi->tx_done || !espi->rx_done) in fsl_espi_cpu_irq()
545 dev_err(espi->dev, in fsl_espi_cpu_irq()
549 dev_err(espi->dev, "Transfer done but rx/tx fifo's aren't empty!\n"); in fsl_espi_cpu_irq()
550 dev_err(espi->dev, "SPIE_RXCNT = %d, SPIE_TXCNT = %d\n", in fsl_espi_cpu_irq()
554 complete(&espi->done); in fsl_espi_cpu_irq()
562 spin_lock(&espi->lock); in fsl_espi_irq()
564 /* Get interrupt events(tx/rx) */ in fsl_espi_irq()
568 spin_unlock(&espi->lock); in fsl_espi_irq()
572 dev_vdbg(espi->dev, "%s: events %x\n", __func__, events); in fsl_espi_irq()
579 spin_unlock(&espi->lock); in fsl_espi_irq()
632 for_each_available_child_of_node(host->dev.of_node, nc) { in fsl_espi_init_regs()
635 if (ret || cs >= host->num_chipselect) in fsl_espi_init_regs()
673 return -ENOMEM; in fsl_espi_probe()
677 host->mode_bits = SPI_RX_DUAL | SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | in fsl_espi_probe()
679 host->dev.of_node = dev->of_node; in fsl_espi_probe()
680 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); in fsl_espi_probe()
681 host->setup = fsl_espi_setup; in fsl_espi_probe()
682 host->cleanup = fsl_espi_cleanup; in fsl_espi_probe()
683 host->transfer_one_message = fsl_espi_do_one_msg; in fsl_espi_probe()
684 host->auto_runtime_pm = true; in fsl_espi_probe()
685 host->max_message_size = fsl_espi_max_message_size; in fsl_espi_probe()
686 host->num_chipselect = num_cs; in fsl_espi_probe()
689 spin_lock_init(&espi->lock); in fsl_espi_probe()
691 espi->dev = dev; in fsl_espi_probe()
692 espi->spibrg = fsl_get_sys_freq(); in fsl_espi_probe()
693 if (espi->spibrg == -1) { in fsl_espi_probe()
695 ret = -EINVAL; in fsl_espi_probe()
699 host->min_speed_hz = DIV_ROUND_UP(espi->spibrg, 4 * 16 * 16); in fsl_espi_probe()
700 host->max_speed_hz = DIV_ROUND_UP(espi->spibrg, 4); in fsl_espi_probe()
702 init_completion(&espi->done); in fsl_espi_probe()
704 espi->reg_base = devm_ioremap_resource(dev, mem); in fsl_espi_probe()
705 if (IS_ERR(espi->reg_base)) { in fsl_espi_probe()
706 ret = PTR_ERR(espi->reg_base); in fsl_espi_probe()
745 struct device_node *np = dev->of_node; in of_fsl_espi_get_chipselects()
749 ret = of_property_read_u32(np, "fsl,espi-num-chipselects", &num_cs); in of_fsl_espi_get_chipselects()
751 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n"); in of_fsl_espi_get_chipselects()
760 struct device *dev = &ofdev->dev; in of_fsl_espi_probe()
761 struct device_node *np = ofdev->dev.of_node; in of_fsl_espi_probe()
768 return -EINVAL; in of_fsl_espi_probe()
773 return -EINVAL; in of_fsl_espi_probe()
781 return -EINVAL; in of_fsl_espi_probe()
788 pm_runtime_disable(&dev->dev); in of_fsl_espi_remove()
826 { .compatible = "fsl,mpc8536-espi" },