1 // SPDX-License-Identifier: GPL-2.0-only
17 #define DRV_NAME		"sflash-falcon"
43 /* Dummy Phase Length */
52 /* SCK Rise-edge Position */
58 /* SCK Fall-edge Position */
82 /* 8-bit multiplexed */
100 	struct device *dev = &spi->dev;  in falcon_sflash_xfer()
101 	struct falcon_sflash *priv = spi_controller_get_devdata(spi->controller);  in falcon_sflash_xfer()
102 	const u8 *txp = t->tx_buf;  in falcon_sflash_xfer()
103 	u8 *rxp = t->rx_buf;  in falcon_sflash_xfer()
104 	unsigned int bytelen = ((8 * t->len + 7) / 8);  in falcon_sflash_xfer()
118 		case state_init: /* detect phase of upper layer sequence */  in falcon_sflash_xfer()
125 					return -ENODATA;  in falcon_sflash_xfer()
134 				priv->sfcmd = ((spi_get_chipselect(spi, 0)  in falcon_sflash_xfer()
137 				priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;  in falcon_sflash_xfer()
138 				priv->sfcmd |= *txp;  in falcon_sflash_xfer()
140 				bytelen--;  in falcon_sflash_xfer()
150 						priv->sfcmd & SFCMD_OPC_MASK);  in falcon_sflash_xfer()
170 		/* collect tx data for address and dummy phase */  in falcon_sflash_xfer()
191 				bytelen--;  in falcon_sflash_xfer()
193 			priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);  in falcon_sflash_xfer()
194 			priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |  in falcon_sflash_xfer()
200 				priv->sfcmd & SFCMD_OPC_MASK,  in falcon_sflash_xfer()
221 			priv->sfcmd |= SFCMD_DIR_WRITE;  in falcon_sflash_xfer()
225 				if (bytelen--)  in falcon_sflash_xfer()
229 					priv->sfcmd &=  in falcon_sflash_xfer()
234 					ltq_ebu_w32(priv->sfcmd  in falcon_sflash_xfer()
239 					priv->sfcmd &= ~(SFCMD_ALEN_MASK  in falcon_sflash_xfer()
249 			priv->sfcmd &= ~SFCMD_DIR_WRITE;  in falcon_sflash_xfer()
253 					priv->sfcmd &=  in falcon_sflash_xfer()
257 				bytelen -= len;  in falcon_sflash_xfer()
258 				ltq_ebu_w32(priv->sfcmd  in falcon_sflash_xfer()
260 				priv->sfcmd &= ~(SFCMD_ALEN_MASK  in falcon_sflash_xfer()
270 						return -EBADE;  in falcon_sflash_xfer()
278 					len--;  in falcon_sflash_xfer()
286 			priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;  in falcon_sflash_xfer()
287 			ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),  in falcon_sflash_xfer()
294 				return -EBADE;  in falcon_sflash_xfer()
314 	if (spi->max_speed_hz >= CLOCK_100M) {  in falcon_sflash_setup()
324 			if (CLOCK_50M / i <= spi->max_speed_hz)  in falcon_sflash_setup()
339 	 * signals on non QUAD flashes  in falcon_sflash_setup()
346 	/* set address wrap around to maximum for 24-bit addresses */  in falcon_sflash_setup()
363 	priv->sfcmd = 0;  in falcon_sflash_xfer_one()
364 	m->actual_length = 0;  in falcon_sflash_xfer_one()
367 	list_for_each_entry(t, &m->transfers, transfer_list) {  in falcon_sflash_xfer_one()
368 		if (list_is_last(&t->transfer_list, &m->transfers))  in falcon_sflash_xfer_one()
372 		ret = falcon_sflash_xfer(m->spi, t, spi_flags);  in falcon_sflash_xfer_one()
378 		m->actual_length += t->len;  in falcon_sflash_xfer_one()
380 		WARN_ON(t->delay.value || t->cs_change);  in falcon_sflash_xfer_one()
384 	m->status = ret;  in falcon_sflash_xfer_one()
396 	host = spi_alloc_host(&pdev->dev, sizeof(*priv));  in falcon_sflash_probe()
398 		return -ENOMEM;  in falcon_sflash_probe()
401 	priv->host = host;  in falcon_sflash_probe()
403 	host->mode_bits = SPI_MODE_3;  in falcon_sflash_probe()
404 	host->flags = SPI_CONTROLLER_HALF_DUPLEX;  in falcon_sflash_probe()
405 	host->setup = falcon_sflash_setup;  in falcon_sflash_probe()
406 	host->transfer_one_message = falcon_sflash_xfer_one;  in falcon_sflash_probe()
407 	host->dev.of_node = pdev->dev.of_node;  in falcon_sflash_probe()
409 	ret = devm_spi_register_controller(&pdev->dev, host);  in falcon_sflash_probe()
416 	{ .compatible = "lantiq,sflash-falcon" },