Lines Matching full:mspi
83 /* MSPI register offsets */
191 MSPI, enumerator
610 /* MSPI helpers */
636 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); in bcm_qspi_hw_set_parms()
670 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1); in bcm_qspi_hw_set_parms()
681 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr); in bcm_qspi_hw_set_parms()
688 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr); in bcm_qspi_hw_set_parms()
784 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; in read_rxram_slot_u8()
793 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | in read_rxram_slot_u16()
794 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); in read_rxram_slot_u16()
803 val = bcm_qspi_read(qspi, MSPI, offset); in read_rxram_slot_u32()
816 msb = bcm_qspi_read(qspi, MSPI, msb_offset); in read_rxram_slot_u64()
818 lsb = bcm_qspi_read(qspi, MSPI, lsb_offset); in read_rxram_slot_u64()
889 bcm_qspi_write(qspi, MSPI, reg_offset, val); in write_txram_slot_u8()
899 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); in write_txram_slot_u16()
900 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); in write_txram_slot_u16()
909 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val)); in write_txram_slot_u32()
921 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb)); in write_txram_slot_u64()
922 bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb)); in write_txram_slot_u64()
927 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); in read_cdram_slot()
932 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val); in write_cdram_slot()
1005 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); in write_to_hw()
1006 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1); in write_to_hw()
1024 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1); in write_to_hw()
1026 /* Must flush previous writes before starting MSPI operation */ in write_to_hw()
1029 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0); in write_to_hw()
1051 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); in bcm_qspi_bspi_exec_mem_op()
1097 * clear soc MSPI and BSPI interrupts and enable in bcm_qspi_bspi_exec_mem_op()
1139 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n"); in bcm_qspi_transfer_one()
1172 /* lets mspi know that this is not last transfer */ in bcm_qspi_mspi_exec_mem_op()
1213 * using MSPI. in bcm_qspi_exec_mem_op()
1222 /* non-aligned and very short transfers are handled by MSPI */ in bcm_qspi_exec_mem_op()
1249 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); in bcm_qspi_mspi_l2_isr()
1255 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status); in bcm_qspi_mspi_l2_isr()
1409 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0); in bcm_qspi_hw_init()
1410 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0); in bcm_qspi_hw_init()
1411 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0); in bcm_qspi_hw_init()
1412 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0); in bcm_qspi_hw_init()
1413 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20); in bcm_qspi_hw_init()
1426 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS); in bcm_qspi_hw_uninit()
1428 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0); in bcm_qspi_hw_uninit()
1430 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0); in bcm_qspi_hw_uninit()
1433 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1); in bcm_qspi_hw_uninit()
1544 "mspi"); in bcm_qspi_probe()
1546 qspi->base[MSPI] = devm_ioremap_resource(dev, res); in bcm_qspi_probe()
1547 if (IS_ERR(qspi->base[MSPI])) in bcm_qspi_probe()
1548 return PTR_ERR(qspi->base[MSPI]); in bcm_qspi_probe()
1597 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV); in bcm_qspi_probe()
1622 /* all mspi, bspi intrs muxed to one L1 intr */ in bcm_qspi_probe()
1718 /* enable MSPI interrupt */ in bcm_qspi_resume()