Lines Matching +full:dout +full:- +full:ports
1 // SPDX-License-Identifier: GPL-2.0
102 #define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103 #define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104 #define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105 #define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106 #define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107 #define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108 #define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109 #define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
204 /* Port numbers are 1 - 14 */
283 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_read()
303 struct regmap *wcd_regmap = ctrl->regmap; in qcom_swrm_ahb_reg_write()
323 *val = readl(ctrl->mmio + reg); in qcom_swrm_cpu_reg_read()
330 writel(val, ctrl->mmio + reg); in qcom_swrm_cpu_reg_write()
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_rd_fifo_avail()
368 } while (fifo_retry_count--); in swrm_wait_for_rd_fifo_avail()
371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__); in swrm_wait_for_rd_fifo_avail()
372 return -EIO; in swrm_wait_for_rd_fifo_avail()
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in swrm_wait_for_wr_fifo_avail()
390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth) in swrm_wait_for_wr_fifo_avail()
394 } while (fifo_retry_count--); in swrm_wait_for_wr_fifo_avail()
396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) { in swrm_wait_for_wr_fifo_avail()
397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__); in swrm_wait_for_wr_fifo_avail()
398 return -EIO; in swrm_wait_for_wr_fifo_avail()
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value); in swrm_wait_for_wr_fifo_done()
418 fifo_retry_count--; in swrm_wait_for_wr_fifo_done()
443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data, in qcom_swrm_cmd_fifo_wr_cmd()
451 reinit_completion(&ctrl->broadcast); in qcom_swrm_cmd_fifo_wr_cmd()
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val); in qcom_swrm_cmd_fifo_wr_cmd()
456 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_cmd_fifo_wr_cmd()
465 ret = wait_for_completion_timeout(&ctrl->broadcast, in qcom_swrm_cmd_fifo_wr_cmd()
484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr); in qcom_swrm_cmd_fifo_rd_cmd()
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val); in qcom_swrm_cmd_fifo_rd_cmd()
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR], in qcom_swrm_cmd_fifo_rd_cmd()
507 if (cmd_id != ctrl->rcmd_id) { in qcom_swrm_cmd_fifo_rd_cmd()
508 if (retry_attempt < (MAX_FIFO_RD_RETRY - 1)) { in qcom_swrm_cmd_fifo_rd_cmd()
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, in qcom_swrm_cmd_fifo_rd_cmd()
513 ctrl->reg_write(ctrl, in qcom_swrm_cmd_fifo_rd_cmd()
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], in qcom_swrm_cmd_fifo_rd_cmd()
524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\ in qcom_swrm_cmd_fifo_rd_cmd()
526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data); in qcom_swrm_cmd_fifo_rd_cmd()
536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_alert_slave_dev_num()
542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK; in qcom_swrm_get_alert_slave_dev_num()
547 return -EINVAL; in qcom_swrm_get_alert_slave_dev_num()
555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val); in qcom_swrm_get_device_status()
556 ctrl->slave_status = val; in qcom_swrm_get_device_status()
563 ctrl->status[i] = s; in qcom_swrm_get_device_status()
573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status); in qcom_swrm_set_slave_dev_num()
579 slave->dev_num = devnum; in qcom_swrm_set_slave_dev_num()
580 mutex_lock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
581 set_bit(devnum, bus->assigned); in qcom_swrm_set_slave_dev_num()
582 mutex_unlock(&bus->bus_lock); in qcom_swrm_set_slave_dev_num()
599 if (!ctrl->status[i]) in qcom_swrm_enumerate()
602 /*SCP_Devid5 - Devid 4*/ in qcom_swrm_enumerate()
603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1); in qcom_swrm_enumerate()
605 /*SCP_Devid3 - DevId 2 Devid 1 Devid 0*/ in qcom_swrm_enumerate()
606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2); in qcom_swrm_enumerate()
617 ctrl->clock_stop_not_supported = false; in qcom_swrm_enumerate()
619 list_for_each_entry_safe(slave, _s, &bus->slaves, node) { in qcom_swrm_enumerate()
622 if (slave->prop.clk_stop_mode1) in qcom_swrm_enumerate()
623 ctrl->clock_stop_not_supported = true; in qcom_swrm_enumerate()
636 complete(&ctrl->enumeration); in qcom_swrm_enumerate()
645 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_wake_irq_handler()
646 if (ret < 0 && ret != -EACCES) { in qcom_swrm_wake_irq_handler()
647 dev_err_ratelimited(ctrl->dev, in qcom_swrm_wake_irq_handler()
650 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_wake_irq_handler()
654 if (ctrl->wake_irq > 0) { in qcom_swrm_wake_irq_handler()
655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) in qcom_swrm_wake_irq_handler()
656 disable_irq_nosync(ctrl->wake_irq); in qcom_swrm_wake_irq_handler()
659 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_wake_irq_handler()
660 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_wake_irq_handler()
672 clk_prepare_enable(ctrl->hclk); in qcom_swrm_irq_handler()
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
676 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
688 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
691 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n"); in qcom_swrm_irq_handler()
698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status); in qcom_swrm_irq_handler()
699 if (ctrl->slave_status == slave_status) { in qcom_swrm_irq_handler()
700 dev_dbg(ctrl->dev, "Slave status not changed %x\n", in qcom_swrm_irq_handler()
704 qcom_swrm_enumerate(&ctrl->bus); in qcom_swrm_irq_handler()
705 sdw_handle_slave_status(&ctrl->bus, ctrl->status); in qcom_swrm_irq_handler()
709 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET; in qcom_swrm_irq_handler()
713 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
715 ctrl->intr_mask); in qcom_swrm_irq_handler()
718 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
721 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
726 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
729 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
734 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
737 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
743 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
746 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
752 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; in qcom_swrm_irq_handler()
756 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
758 ctrl->intr_mask); in qcom_swrm_irq_handler()
761 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
764 ctrl->intr_mask &= in qcom_swrm_irq_handler()
766 ctrl->reg_write(ctrl, in qcom_swrm_irq_handler()
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_irq_handler()
768 ctrl->intr_mask); in qcom_swrm_irq_handler()
771 complete(&ctrl->broadcast); in qcom_swrm_irq_handler()
780 ctrl->reg_read(ctrl, in qcom_swrm_irq_handler()
781 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], in qcom_swrm_irq_handler()
783 dev_err(ctrl->dev, in qcom_swrm_irq_handler()
791 dev_err_ratelimited(ctrl->dev, in qcom_swrm_irq_handler()
798 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_irq_handler()
800 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS], in qcom_swrm_irq_handler()
802 intr_sts_masked = intr_sts & ctrl->intr_mask; in qcom_swrm_irq_handler()
805 clk_disable_unprepare(ctrl->hclk); in qcom_swrm_irq_handler()
815 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_FRAME_GEN_ENABLED], in swrm_wait_for_frame_gen_enabled()
821 } while (retry--); in swrm_wait_for_frame_gen_enabled()
823 dev_err(ctrl->dev, "%s: link status not %s\n", __func__, in swrm_wait_for_frame_gen_enabled()
834 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index); in qcom_swrm_init()
835 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index); in qcom_swrm_init()
837 reset_control_reset(ctrl->audio_cgcr); in qcom_swrm_init()
839 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
842 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1); in qcom_swrm_init()
844 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK; in qcom_swrm_init()
846 if (ctrl->version < SWRM_VERSION_2_0_0) in qcom_swrm_init()
847 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR], in qcom_swrm_init()
851 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val); in qcom_swrm_init()
853 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
855 if (ctrl->version == SWRM_VERSION_1_7_0) { in qcom_swrm_init()
856 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
857 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, in qcom_swrm_init()
859 } else if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_init()
860 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU); in qcom_swrm_init()
861 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL, in qcom_swrm_init()
864 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START); in qcom_swrm_init()
868 if (ctrl->version >= SWRM_VERSION_1_5_1) { in qcom_swrm_init()
869 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
873 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, in qcom_swrm_init()
878 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK); in qcom_swrm_init()
881 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
884 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR], in qcom_swrm_init()
888 if (ctrl->mmio) { in qcom_swrm_init()
889 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN], in qcom_swrm_init()
894 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, in qcom_swrm_init()
899 ctrl->slave_status = 0; in qcom_swrm_init()
900 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_init()
901 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val); in qcom_swrm_init()
902 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val); in qcom_swrm_init()
911 if (ctrl->version >= SWRM_VERSION_2_0_0) { in qcom_swrm_read_prop()
912 bus->multi_link = true; in qcom_swrm_read_prop()
913 bus->hw_sync_min_links = 3; in qcom_swrm_read_prop()
925 if (msg->flags == SDW_MSG_FLAG_READ) { in qcom_swrm_xfer_msg()
926 for (i = 0; i < msg->len;) { in qcom_swrm_xfer_msg()
927 if ((msg->len - i) < QCOM_SWRM_MAX_RD_LEN) in qcom_swrm_xfer_msg()
928 len = msg->len - i; in qcom_swrm_xfer_msg()
932 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num, in qcom_swrm_xfer_msg()
933 msg->addr + i, len, in qcom_swrm_xfer_msg()
934 &msg->buf[i]); in qcom_swrm_xfer_msg()
940 } else if (msg->flags == SDW_MSG_FLAG_WRITE) { in qcom_swrm_xfer_msg()
941 for (i = 0; i < msg->len; i++) { in qcom_swrm_xfer_msg()
942 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i], in qcom_swrm_xfer_msg()
943 msg->dev_num, in qcom_swrm_xfer_msg()
944 msg->addr + i); in qcom_swrm_xfer_msg()
955 u32 reg = SWRM_MCP_FRAME_CTRL_BANK_ADDR(bus->params.next_bank); in qcom_swrm_pre_bank_switch()
959 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_pre_bank_switch()
961 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
962 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK); in qcom_swrm_pre_bank_switch()
964 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_pre_bank_switch()
973 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num), in qcom_swrm_port_params()
974 p_params->bps - 1); in qcom_swrm_port_params()
985 int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank); in qcom_swrm_transport_params()
988 pcfg = &ctrl->pconfig[params->port_num]; in qcom_swrm_transport_params()
990 value = pcfg->off1 << SWRM_DP_PORT_CTRL_OFFSET1_SHFT; in qcom_swrm_transport_params()
991 value |= pcfg->off2 << SWRM_DP_PORT_CTRL_OFFSET2_SHFT; in qcom_swrm_transport_params()
992 value |= pcfg->si & 0xff; in qcom_swrm_transport_params()
994 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
998 if (pcfg->si > 0xff) { in qcom_swrm_transport_params()
999 value = (pcfg->si >> 8) & 0xff; in qcom_swrm_transport_params()
1000 reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1001 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1006 if (pcfg->lane_control != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1007 reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1008 value = pcfg->lane_control; in qcom_swrm_transport_params()
1009 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1014 if (pcfg->blk_group_count != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1015 reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1016 value = pcfg->blk_group_count; in qcom_swrm_transport_params()
1017 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1022 if (pcfg->hstart != SWR_INVALID_PARAM in qcom_swrm_transport_params()
1023 && pcfg->hstop != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1024 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1025 value = (pcfg->hstop << 4) | pcfg->hstart; in qcom_swrm_transport_params()
1026 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1028 reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1030 ret = ctrl->reg_write(ctrl, reg, value); in qcom_swrm_transport_params()
1036 if (pcfg->bp_mode != SWR_INVALID_PARAM) { in qcom_swrm_transport_params()
1037 reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank); in qcom_swrm_transport_params()
1038 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode); in qcom_swrm_transport_params()
1049 u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank); in qcom_swrm_port_enable()
1053 ctrl->reg_read(ctrl, reg, &val); in qcom_swrm_port_enable()
1055 if (enable_ch->enable) in qcom_swrm_port_enable()
1056 val |= (enable_ch->ch_mask << SWRM_DP_PORT_CTRL_EN_CHAN_SHFT); in qcom_swrm_port_enable()
1060 return ctrl->reg_write(ctrl, reg, val); in qcom_swrm_port_enable()
1086 list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) { in qcom_swrm_compute_params()
1087 list_for_each_entry(p_rt, &m_rt->port_list, port_node) { in qcom_swrm_compute_params()
1088 pcfg = &ctrl->pconfig[p_rt->num]; in qcom_swrm_compute_params()
1089 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1090 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1091 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1092 p_rt->num, pcfg->word_length + 1, in qcom_swrm_compute_params()
1099 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_compute_params()
1100 slave = s_rt->slave; in qcom_swrm_compute_params()
1101 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_compute_params()
1102 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_compute_params()
1103 /* port config starts at offset 0 so -1 from actual port number */ in qcom_swrm_compute_params()
1105 pcfg = &ctrl->pconfig[m_port]; in qcom_swrm_compute_params()
1107 pcfg = &ctrl->pconfig[i]; in qcom_swrm_compute_params()
1108 p_rt->transport_params.port_num = p_rt->num; in qcom_swrm_compute_params()
1109 p_rt->transport_params.sample_interval = in qcom_swrm_compute_params()
1110 pcfg->si + 1; in qcom_swrm_compute_params()
1111 p_rt->transport_params.offset1 = pcfg->off1; in qcom_swrm_compute_params()
1112 p_rt->transport_params.offset2 = pcfg->off2; in qcom_swrm_compute_params()
1113 p_rt->transport_params.blk_pkg_mode = pcfg->bp_mode; in qcom_swrm_compute_params()
1114 p_rt->transport_params.blk_grp_ctrl = pcfg->blk_group_count; in qcom_swrm_compute_params()
1116 p_rt->transport_params.hstart = pcfg->hstart; in qcom_swrm_compute_params()
1117 p_rt->transport_params.hstop = pcfg->hstop; in qcom_swrm_compute_params()
1118 p_rt->transport_params.lane_ctrl = pcfg->lane_control; in qcom_swrm_compute_params()
1119 if (pcfg->word_length != SWR_INVALID_PARAM) { in qcom_swrm_compute_params()
1120 sdw_fill_port_params(&p_rt->port_params, in qcom_swrm_compute_params()
1121 p_rt->num, in qcom_swrm_compute_params()
1122 pcfg->word_length + 1, in qcom_swrm_compute_params()
1145 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1147 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_free_ports()
1148 port_mask = &ctrl->port_mask; in qcom_swrm_stream_free_ports()
1149 list_for_each_entry(p_rt, &m_rt->port_list, port_node) in qcom_swrm_stream_free_ports()
1150 clear_bit(p_rt->num, port_mask); in qcom_swrm_stream_free_ports()
1153 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_free_ports()
1179 sconfig.type = stream->type; in qcom_swrm_stream_alloc_ports()
1182 mutex_lock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1183 list_for_each_entry(m_rt, &stream->master_list, stream_node) { in qcom_swrm_stream_alloc_ports()
1186 * Allocate ports only for devices connected to this master. in qcom_swrm_stream_alloc_ports()
1187 * Such devices will have ports allocated by their own master in qcom_swrm_stream_alloc_ports()
1190 if (ctrl->bus.id != m_rt->bus->id) in qcom_swrm_stream_alloc_ports()
1193 port_mask = &ctrl->port_mask; in qcom_swrm_stream_alloc_ports()
1194 maxport = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_stream_alloc_ports()
1197 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in qcom_swrm_stream_alloc_ports()
1198 slave = s_rt->slave; in qcom_swrm_stream_alloc_ports()
1199 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in qcom_swrm_stream_alloc_ports()
1200 m_port = slave->m_port_map[p_rt->num]; in qcom_swrm_stream_alloc_ports()
1201 /* Port numbers start from 1 - 14*/ in qcom_swrm_stream_alloc_ports()
1208 dev_err(ctrl->dev, "All ports busy\n"); in qcom_swrm_stream_alloc_ports()
1209 ret = -EBUSY; in qcom_swrm_stream_alloc_ports()
1214 pconfig[nports].ch_mask = p_rt->ch_mask; in qcom_swrm_stream_alloc_ports()
1220 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig, in qcom_swrm_stream_alloc_ports()
1223 mutex_unlock(&ctrl->port_lock); in qcom_swrm_stream_alloc_ports()
1232 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_params()
1233 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_params()
1237 substream->stream); in qcom_swrm_hw_params()
1247 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_hw_free()
1248 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id]; in qcom_swrm_hw_free()
1251 sdw_stream_remove_master(&ctrl->bus, sruntime); in qcom_swrm_hw_free()
1259 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_set_sdw_stream()
1261 ctrl->sruntime[dai->id] = stream; in qcom_swrm_set_sdw_stream()
1268 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_get_sdw_stream()
1270 return ctrl->sruntime[dai->id]; in qcom_swrm_get_sdw_stream()
1276 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_startup()
1279 ret = pm_runtime_get_sync(ctrl->dev); in qcom_swrm_startup()
1280 if (ret < 0 && ret != -EACCES) { in qcom_swrm_startup()
1281 dev_err_ratelimited(ctrl->dev, in qcom_swrm_startup()
1284 pm_runtime_put_noidle(ctrl->dev); in qcom_swrm_startup()
1294 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev); in qcom_swrm_shutdown()
1297 pm_runtime_mark_last_busy(ctrl->dev); in qcom_swrm_shutdown()
1298 pm_runtime_put_autosuspend(ctrl->dev); in qcom_swrm_shutdown()
1317 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_register_dais()
1320 struct device *dev = ctrl->dev; in qcom_swrm_register_dais()
1326 return -ENOMEM; in qcom_swrm_register_dais()
1331 return -ENOMEM; in qcom_swrm_register_dais()
1333 if (i < ctrl->num_dout_ports) in qcom_swrm_register_dais()
1338 stream->channels_min = 1; in qcom_swrm_register_dais()
1339 stream->channels_max = 1; in qcom_swrm_register_dais()
1340 stream->rates = SNDRV_PCM_RATE_48000; in qcom_swrm_register_dais()
1341 stream->formats = SNDRV_PCM_FMTBIT_S16_LE; in qcom_swrm_register_dais()
1347 return devm_snd_soc_register_component(ctrl->dev, in qcom_swrm_register_dais()
1354 struct device_node *np = ctrl->dev->of_node; in qcom_swrm_get_port_config()
1367 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val); in qcom_swrm_get_port_config()
1369 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val); in qcom_swrm_get_port_config()
1370 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val); in qcom_swrm_get_port_config()
1372 ret = of_property_read_u32(np, "qcom,din-ports", &val); in qcom_swrm_get_port_config()
1376 if (val > ctrl->num_din_ports) in qcom_swrm_get_port_config()
1377 return -EINVAL; in qcom_swrm_get_port_config()
1379 ctrl->num_din_ports = val; in qcom_swrm_get_port_config()
1381 ret = of_property_read_u32(np, "qcom,dout-ports", &val); in qcom_swrm_get_port_config()
1385 if (val > ctrl->num_dout_ports) in qcom_swrm_get_port_config()
1386 return -EINVAL; in qcom_swrm_get_port_config()
1388 ctrl->num_dout_ports = val; in qcom_swrm_get_port_config()
1390 nports = ctrl->num_dout_ports + ctrl->num_din_ports; in qcom_swrm_get_port_config()
1392 return -EINVAL; in qcom_swrm_get_port_config()
1394 /* Valid port numbers are from 1-14, so mask out port 0 explicitly */ in qcom_swrm_get_port_config()
1395 set_bit(0, &ctrl->port_mask); in qcom_swrm_get_port_config()
1397 ret = of_property_read_u8_array(np, "qcom,ports-offset1", in qcom_swrm_get_port_config()
1402 ret = of_property_read_u8_array(np, "qcom,ports-offset2", in qcom_swrm_get_port_config()
1407 ret = of_property_read_u8_array(np, "qcom,ports-sinterval-low", in qcom_swrm_get_port_config()
1410 ret = of_property_read_u16_array(np, "qcom,ports-sinterval", in qcom_swrm_get_port_config()
1417 ret = of_property_read_u8_array(np, "qcom,ports-block-pack-mode", in qcom_swrm_get_port_config()
1420 if (ctrl->version <= SWRM_VERSION_1_3_0) in qcom_swrm_get_port_config()
1427 of_property_read_u8_array(np, "qcom,ports-hstart", hstart, nports); in qcom_swrm_get_port_config()
1430 of_property_read_u8_array(np, "qcom,ports-hstop", hstop, nports); in qcom_swrm_get_port_config()
1433 of_property_read_u8_array(np, "qcom,ports-word-length", word_length, nports); in qcom_swrm_get_port_config()
1436 of_property_read_u8_array(np, "qcom,ports-block-group-count", blk_group_count, nports); in qcom_swrm_get_port_config()
1439 of_property_read_u8_array(np, "qcom,ports-lane-control", lane_control, nports); in qcom_swrm_get_port_config()
1442 /* Valid port number range is from 1-14 */ in qcom_swrm_get_port_config()
1444 ctrl->pconfig[i + 1].si = si[i]; in qcom_swrm_get_port_config()
1446 ctrl->pconfig[i + 1].si = ((u8 *)si)[i]; in qcom_swrm_get_port_config()
1447 ctrl->pconfig[i + 1].off1 = off1[i]; in qcom_swrm_get_port_config()
1448 ctrl->pconfig[i + 1].off2 = off2[i]; in qcom_swrm_get_port_config()
1449 ctrl->pconfig[i + 1].bp_mode = bp_mode[i]; in qcom_swrm_get_port_config()
1450 ctrl->pconfig[i + 1].hstart = hstart[i]; in qcom_swrm_get_port_config()
1451 ctrl->pconfig[i + 1].hstop = hstop[i]; in qcom_swrm_get_port_config()
1452 ctrl->pconfig[i + 1].word_length = word_length[i]; in qcom_swrm_get_port_config()
1453 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i]; in qcom_swrm_get_port_config()
1454 ctrl->pconfig[i + 1].lane_control = lane_control[i]; in qcom_swrm_get_port_config()
1463 struct qcom_swrm_ctrl *ctrl = s_file->private; in swrm_reg_show()
1466 ret = pm_runtime_get_sync(ctrl->dev); in swrm_reg_show()
1467 if (ret < 0 && ret != -EACCES) { in swrm_reg_show()
1468 dev_err_ratelimited(ctrl->dev, in swrm_reg_show()
1471 pm_runtime_put_noidle(ctrl->dev); in swrm_reg_show()
1475 for (reg = 0; reg <= ctrl->max_reg; reg += 4) { in swrm_reg_show()
1476 ctrl->reg_read(ctrl, reg, ®_val); in swrm_reg_show()
1479 pm_runtime_mark_last_busy(ctrl->dev); in swrm_reg_show()
1480 pm_runtime_put_autosuspend(ctrl->dev); in swrm_reg_show()
1490 struct device *dev = &pdev->dev;
1500 return -ENOMEM;
1503 ctrl->max_reg = data->max_reg;
1504 ctrl->reg_layout = data->reg_layout;
1505 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1506 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1508 if (dev->parent->bus == &slimbus_bus) {
1512 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1513 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1514 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1515 if (!ctrl->regmap)
1516 return -EINVAL;
1518 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1519 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1520 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1521 if (IS_ERR(ctrl->mmio))
1522 return PTR_ERR(ctrl->mmio);
1525 if (data->sw_clk_gate_required) {
1526 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1527 if (IS_ERR(ctrl->audio_cgcr)) {
1529 ret = PTR_ERR(ctrl->audio_cgcr);
1534 ctrl->irq = of_irq_get(dev->of_node, 0);
1535 if (ctrl->irq < 0) {
1536 ret = ctrl->irq;
1540 ctrl->hclk = devm_clk_get(dev, "iface");
1541 if (IS_ERR(ctrl->hclk)) {
1542 ret = dev_err_probe(dev, PTR_ERR(ctrl->hclk), "unable to get iface clock\n");
1546 clk_prepare_enable(ctrl->hclk);
1548 ctrl->dev = dev;
1549 dev_set_drvdata(&pdev->dev, ctrl);
1550 mutex_init(&ctrl->port_lock);
1551 init_completion(&ctrl->broadcast);
1552 init_completion(&ctrl->enumeration);
1554 ctrl->bus.ops = &qcom_swrm_ops;
1555 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1556 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1557 ctrl->bus.clk_stop_timeout = 300;
1563 params = &ctrl->bus.params;
1564 params->max_dr_freq = DEFAULT_CLK_FREQ;
1565 params->curr_dr_freq = DEFAULT_CLK_FREQ;
1566 params->col = data->default_cols;
1567 params->row = data->default_rows;
1568 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1569 params->curr_bank = val & SWRM_MCP_STATUS_BANK_NUM_MASK;
1570 params->next_bank = !params->curr_bank;
1572 prop = &ctrl->bus.prop;
1573 prop->max_clk_freq = DEFAULT_CLK_FREQ;
1574 prop->num_clk_gears = 0;
1575 prop->num_clk_freq = MAX_FREQ_NUM;
1576 prop->clk_freq = &qcom_swrm_freq_tbl[0];
1577 prop->default_col = data->default_cols;
1578 prop->default_row = data->default_rows;
1580 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1582 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1592 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1593 if (ctrl->wake_irq > 0) {
1594 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1604 ctrl->bus.controller_id = -1;
1606 if (ctrl->version > SWRM_VERSION_1_3_0) {
1607 ctrl->reg_read(ctrl, SWRM_COMP_MASTER_ID, &val);
1608 ctrl->bus.controller_id = val;
1611 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1619 wait_for_completion_timeout(&ctrl->enumeration,
1626 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1627 ctrl->version & 0xffff);
1636 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1637 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1644 sdw_bus_master_delete(&ctrl->bus);
1646 clk_disable_unprepare(ctrl->hclk);
1653 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1655 sdw_bus_master_delete(&ctrl->bus);
1656 clk_disable_unprepare(ctrl->hclk);
1664 if (ctrl->wake_irq > 0) {
1665 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1666 disable_irq_nosync(ctrl->wake_irq);
1669 clk_prepare_enable(ctrl->hclk);
1671 if (ctrl->clock_stop_not_supported) {
1672 reinit_completion(&ctrl->enumeration);
1673 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1680 dev_err(ctrl->dev, "link failed to connect\n");
1683 wait_for_completion_timeout(&ctrl->enumeration,
1686 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1688 reset_control_reset(ctrl->audio_cgcr);
1690 if (ctrl->version == SWRM_VERSION_1_7_0) {
1691 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1692 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1694 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1695 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1696 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1699 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1701 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1704 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1705 if (ctrl->version < SWRM_VERSION_2_0_0)
1706 ctrl->reg_write(ctrl,
1707 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1708 ctrl->intr_mask);
1709 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1710 ctrl->intr_mask);
1714 dev_err(ctrl->dev, "link failed to connect\n");
1716 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1718 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1730 if (!ctrl->clock_stop_not_supported) {
1732 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1733 if (ctrl->version < SWRM_VERSION_2_0_0)
1734 ctrl->reg_write(ctrl,
1735 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1736 ctrl->intr_mask);
1737 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1738 ctrl->intr_mask);
1740 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1741 if (ret < 0 && ret != -ENODATA) {
1746 ret = sdw_bus_clk_stop(&ctrl->bus);
1747 if (ret < 0 && ret != -ENODATA) {
1753 clk_disable_unprepare(ctrl->hclk);
1757 if (ctrl->wake_irq > 0) {
1758 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1759 enable_irq(ctrl->wake_irq);
1770 { .compatible = "qcom,soundwire-v1.3.0", .data = &swrm_v1_3_data },
1771 { .compatible = "qcom,soundwire-v1.5.1", .data = &swrm_v1_5_data },
1772 { .compatible = "qcom,soundwire-v1.6.0", .data = &swrm_v1_6_data },
1773 { .compatible = "qcom,soundwire-v1.7.0", .data = &swrm_v1_5_data },
1774 { .compatible = "qcom,soundwire-v2.0.0", .data = &swrm_v2_0_data },
1784 .name = "qcom-soundwire",