75 	void __iomem *s = sdw->link_res->shim;  in intel_reg_show()
204  * shim ops
209 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_glue_to_master_ip()  local
214 	ioctl = intel_readw(shim,  SDW_SHIM_IOCTL(link_id));  in intel_shim_glue_to_master_ip()
217 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_glue_to_master_ip()
221 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_glue_to_master_ip()
225 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_glue_to_master_ip()
230 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_glue_to_master_ip()
240 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_master_ip_to_glue()  local
244 	ioctl = intel_readw(shim, SDW_SHIM_IOCTL(link_id));  in intel_shim_master_ip_to_glue()
247 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_master_ip_to_glue()
251 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_master_ip_to_glue()
260 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_init()  local
264 	/* Initialize Shim */  in intel_shim_init()
266 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_init()
270 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_init()
274 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_init()
278 	intel_writew(shim, SDW_SHIM_IOCTL(link_id), ioctl);  in intel_shim_init()
283 	act = intel_readw(shim, SDW_SHIM_CTMCTL(link_id));  in intel_shim_init()
287 	intel_writew(shim, SDW_SHIM_CTMCTL(link_id), act);  in intel_shim_init()
293 	void __iomem *shim;  in intel_shim_check_wake()  local
296 	shim = sdw->link_res->shim;  in intel_shim_check_wake()
297 	wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);  in intel_shim_check_wake()
304 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_wake()  local
309 	wake_en = intel_readw(shim, SDW_SHIM_WAKEEN);  in intel_shim_wake()
314 		intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);  in intel_shim_wake()
318 		intel_writew(shim, SDW_SHIM_WAKEEN, wake_en);  in intel_shim_wake()
321 		wake_sts = intel_readw(shim, SDW_SHIM_WAKESTS);  in intel_shim_wake()
323 		intel_writew(shim, SDW_SHIM_WAKESTS, wake_sts);  in intel_shim_wake()
330 	void __iomem *shim = sdw->link_res->shim;  in intel_check_cmdsync_unlocked()  local
333 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_check_cmdsync_unlocked()
340 	void __iomem *shim = sdw->link_res->shim;  in intel_link_power_up()  local
365 	lcap_mlcs = intel_readl(shim, SDW_SHIM_LCAP) & SDW_SHIM_LCAP_MLCS_MASK;  in intel_link_power_up()
400 		sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_link_power_up()
405 		intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_link_power_up()
408 		link_control = intel_readl(shim, SDW_SHIM_LCTL);  in intel_link_power_up()
416 		ret = intel_set_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);  in intel_link_power_up()
423 		ret = intel_wait_bit(shim, SDW_SHIM_SYNC,  in intel_link_power_up()
433 			link_control = intel_readl(shim, SDW_SHIM_LCTL);  in intel_link_power_up()
435 			intel_writel(shim, SDW_SHIM_LCTL, link_control);  in intel_link_power_up()
455 	void __iomem *shim = sdw->link_res->shim;  in intel_link_power_down()  local
476 		link_control = intel_readl(shim, SDW_SHIM_LCTL);  in intel_link_power_down()
484 		ret = intel_clear_bit(shim, SDW_SHIM_LCTL, link_control, cpa_mask);  in intel_link_power_down()
502 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_sync_arm()  local
508 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_shim_sync_arm()
510 	intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_shim_sync_arm()
517 	void __iomem *shim = sdw->link_res->shim;  in intel_shim_sync_go_unlocked()  local
521 	sync_reg = intel_readl(shim, SDW_SHIM_SYNC);  in intel_shim_sync_go_unlocked()
530 	intel_writel(shim, SDW_SHIM_SYNC, sync_reg);  in intel_shim_sync_go_unlocked()
554 	void __iomem *shim = sdw->link_res->shim;  in intel_pdi_init()  local
559 	pcm_cap = intel_readw(shim, SDW_SHIM_PCMSCAP(link_id));  in intel_pdi_init()
572 	void __iomem *shim = sdw->link_res->shim;  in intel_pdi_get_ch_cap()  local
576 	count = intel_readw(shim, SDW_SHIM_PCMSYCHC(link_id, pdi_num));  in intel_pdi_get_ch_cap()
628 	void __iomem *shim = sdw->link_res->shim;  in intel_pdi_shim_configure()  local
638 	 * Program stream parameters to stream SHIM register  in intel_pdi_shim_configure()
653 	intel_writew(shim, SDW_SHIM_PCMSYCHM(link_id, pdi->num), pdi_conf);  in intel_pdi_shim_configure()
747 	/* do run-time configurations for SHIM, ALH and PDI/PORT */  in intel_hw_params()
814 		 * need to reinitialize the SHIM/ALH/Cadence IP.  in intel_prepare()
816 		 * but in those cases we cannot touch ALH/SHIM  in intel_prepare()
914 		 * In the case of xruns, the DMAs and SHIM registers cannot be touched,  in intel_trigger()
915 		 * but for resume operations the DMAs and SHIM registers need to be initialized.  in intel_trigger()