35 	writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);  in amd_init_sdw_manager()
36 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,  in amd_init_sdw_manager()
42 	writel(AMD_SDW_BUS_RESET_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);  in amd_init_sdw_manager()
43 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val,  in amd_init_sdw_manager()
48 	writel(AMD_SDW_BUS_RESET_CLEAR_REQ, amd_manager->mmio + ACP_SW_BUS_RESET_CTRL);  in amd_init_sdw_manager()
49 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_BUS_RESET_CTRL, val, !val,  in amd_init_sdw_manager()
57 	writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);  in amd_init_sdw_manager()
58 	return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,  in amd_init_sdw_manager()
66 	writel(AMD_SDW_ENABLE, amd_manager->mmio + ACP_SW_EN);  in amd_enable_sdw_manager()
67 	return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, val, ACP_DELAY_US,  in amd_enable_sdw_manager()
75 	writel(AMD_SDW_DISABLE, amd_manager->mmio + ACP_SW_EN);  in amd_disable_sdw_manager()
81 	val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_disable_sdw_manager()
84 	return readl_poll_timeout(amd_manager->mmio + ACP_SW_EN_STATUS, val, !val, ACP_DELAY_US,  in amd_disable_sdw_manager()
97 	writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +  in amd_enable_sdw_interrupts()
99 	writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +  in amd_enable_sdw_interrupts()
101 	writel(AMD_SDW_IRQ_ERROR_MASK, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);  in amd_enable_sdw_interrupts()
114 	writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);  in amd_disable_sdw_interrupts()
115 	writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);  in amd_disable_sdw_interrupts()
116 	writel(0x00, amd_manager->mmio + ACP_SW_ERROR_INTR_MASK);  in amd_disable_sdw_interrupts()
130 	writel(frame_size, amd_manager->mmio + ACP_SW_FRAMESIZE);  in amd_sdw_set_frameshape()
137 	wake_ctrl = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);  in amd_sdw_wake_enable()
143 	writel(wake_ctrl, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);  in amd_sdw_wake_enable()
180 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,  in amd_sdw_send_cmd_get_resp()
190 		writel(0x00, amd_manager->mmio + ACP_SW_IMM_CMD_STS);  in amd_sdw_send_cmd_get_resp()
192 	writel(upper_data, amd_manager->mmio + ACP_SW_IMM_CMD_UPPER_WORD);  in amd_sdw_send_cmd_get_resp()
193 	writel(lower_data, amd_manager->mmio + ACP_SW_IMM_CMD_LOWER_QWORD);  in amd_sdw_send_cmd_get_resp()
195 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,  in amd_sdw_send_cmd_get_resp()
202 	upper_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_UPPER_WORD);  in amd_sdw_send_cmd_get_resp()
203 	lower_resp = readl(amd_manager->mmio + ACP_SW_IMM_RESP_LOWER_QWORD);  in amd_sdw_send_cmd_get_resp()
205 	writel(AMD_SDW_IMM_RES_VALID, amd_manager->mmio + ACP_SW_IMM_CMD_STS);  in amd_sdw_send_cmd_get_resp()
206 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_IMM_CMD_STS, sts,  in amd_sdw_send_cmd_get_resp()
447 	dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);  in amd_sdw_port_params()
451 	writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);  in amd_sdw_port_params()
486 	writel(AMD_SDW_SSP_COUNTER_VAL, amd_manager->mmio + ACP_SW_SSP_COUNTER);  in amd_sdw_transport_params()
488 	dpn_frame_fmt = readl(amd_manager->mmio + frame_fmt_reg);  in amd_sdw_transport_params()
492 	writel(dpn_frame_fmt, amd_manager->mmio + frame_fmt_reg);  in amd_sdw_transport_params()
495 	writel(dpn_sampleinterval, amd_manager->mmio + sample_int_reg);  in amd_sdw_transport_params()
499 	writel(dpn_hctrl, amd_manager->mmio + hctrl_dp0_reg);  in amd_sdw_transport_params()
503 	writel(dpn_offsetctrl, amd_manager->mmio + offset_reg);  in amd_sdw_transport_params()
509 	dpn_lanectrl = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);  in amd_sdw_transport_params()
511 	writel(dpn_lanectrl, amd_manager->mmio + lane_ctrl_ch_en_reg);  in amd_sdw_transport_params()
538 	dpn_ch_enable = readl(amd_manager->mmio + lane_ctrl_ch_en_reg);  in amd_sdw_port_enable()
541 		writel(dpn_ch_enable, amd_manager->mmio + lane_ctrl_ch_en_reg);  in amd_sdw_port_enable()
543 		writel(0, amd_manager->mmio + lane_ctrl_ch_en_reg);  in amd_sdw_port_enable()
775 		writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_0TO7);  in amd_sdw_update_slave_status_work()
776 		writel(0, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_MASK_8TO11);  in amd_sdw_update_slave_status_work()
790 			writel(AMD_SDW_IRQ_MASK_0TO7, amd_manager->mmio +  in amd_sdw_update_slave_status_work()
792 			writel(AMD_SDW_IRQ_MASK_8TO11, amd_manager->mmio +  in amd_sdw_update_slave_status_work()
832 	writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);  in amd_sdw_process_wake_event()
842 	status_change_8to11 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);  in amd_sdw_irq_thread()
843 	status_change_0to7 = readl(amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);  in amd_sdw_irq_thread()
857 	writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_8TO11);  in amd_sdw_irq_thread()
858 	writel(0x00, amd_manager->mmio + ACP_SW_STATE_CHANGE_STATUS_0TO7);  in amd_sdw_irq_thread()
906 		dev_err(dev, "mmio not found\n");  in amd_sdw_manager_probe()
910 	amd_manager->mmio = amd_manager->acp_mmio +  in amd_sdw_manager_probe()
998 	ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,  in amd_sdw_clock_stop()
1019 		val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_sdw_clock_stop_exit()
1021 		writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_sdw_clock_stop_exit()
1022 		ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,  in amd_sdw_clock_stop_exit()
1026 			writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_sdw_clock_stop_exit()
1164 		val = readl(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_resume_runtime()
1167 			writel(val, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_resume_runtime()
1168 			ret = readl_poll_timeout(amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL, val,  in amd_resume_runtime()
1172 				writel(0, amd_manager->mmio + ACP_SW_CLK_RESUME_CTRL);  in amd_resume_runtime()