1 // SPDX-License-Identifier: GPL-2.0+
3  * Voltage regulators coupler for NVIDIA Tegra30
4  * Copyright (C) 2019 GRATE-DRIVER project
7  * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt)	"tegra voltage-coupler: " fmt
52 	 * Tegra30 SoC has critical DVFS-capable devices that are  in tegra30_core_limit()
53 	 * permanently-active or active at a boot time, like EMC  in tegra30_core_limit()
59 	 * the state of all DVFS-critical CORE devices is synced.  in tegra30_core_limit()
61 	if (tegra_pmc_core_domain_state_synced() && !tegra->sys_reboot_mode) {  in tegra30_core_limit()
66 	if (tegra->core_min_uV > 0)  in tegra30_core_limit()
67 		return tegra->core_min_uV;  in tegra30_core_limit()
82 	 * whatever maximum value defined via board's device-tree.  in tegra30_core_limit()
84 	tegra->core_min_uV = core_max_uV;  in tegra30_core_limit()
86 	pr_info("core voltage initialized to %duV\n", tegra->core_min_uV);  in tegra30_core_limit()
88 	return tegra->core_min_uV;  in tegra30_core_limit()
117 	return -EINVAL;  in tegra30_core_cpu_limit()
186 	 * by the CORE voltage. This applies to all Tegra30 SoC's.  in tegra30_voltage_update()
188 	max_spread = cpu_rdev->constraints->max_spread[0];  in tegra30_voltage_update()
189 	cpu_max_step = cpu_rdev->constraints->max_uV_step;  in tegra30_voltage_update()
190 	core_max_step = core_rdev->constraints->max_uV_step;  in tegra30_voltage_update()
193 		pr_err_once("cpu-core max-spread is undefined in device-tree\n");  in tegra30_voltage_update()
198 		pr_err_once("cpu max-step is undefined in device-tree\n");  in tegra30_voltage_update()
203 		pr_err_once("core max-step is undefined in device-tree\n");  in tegra30_voltage_update()
222 	if (tegra->sys_suspend_mode)  in tegra30_voltage_update()
230 	cpu_min_uV = core_min_uV - max_spread;  in tegra30_voltage_update()
251 	if (!tegra->cpu_min_uV)  in tegra30_voltage_update()
252 		tegra->cpu_min_uV = cpu_uV;  in tegra30_voltage_update()
278 	if (tegra->sys_reboot_mode)  in tegra30_voltage_update()
279 		cpu_min_uV = max(cpu_min_uV, tegra->cpu_min_uV);  in tegra30_voltage_update()
282 	if (tegra->sys_suspend_mode)  in tegra30_voltage_update()
296 			cpu_target_uV = max(cpu_uV - cpu_max_step, cpu_min_uV);  in tegra30_voltage_update()
297 			cpu_target_uV = max(core_uV - max_spread, cpu_target_uV);  in tegra30_voltage_update()
322 			core_target_uV = max(core_target_uV, core_uV - core_max_step);  in tegra30_voltage_update()
346 	struct regulator_dev *core_rdev = tegra->core_rdev;  in tegra30_regulator_balance_voltage()
347 	struct regulator_dev *cpu_rdev = tegra->cpu_rdev;  in tegra30_regulator_balance_voltage()
351 		return -EINVAL;  in tegra30_regulator_balance_voltage()
354 	tegra->sys_reboot_mode = READ_ONCE(tegra->sys_reboot_mode_req);  in tegra30_regulator_balance_voltage()
355 	tegra->sys_suspend_mode = READ_ONCE(tegra->sys_suspend_mode_req);  in tegra30_regulator_balance_voltage()
365 	if (!tegra->core_rdev || !tegra->cpu_rdev)  in tegra30_regulator_prepare_suspend()
375 	WRITE_ONCE(tegra->sys_suspend_mode_req, sys_suspend_mode);  in tegra30_regulator_prepare_suspend()
377 	err = regulator_sync_voltage_rdev(tegra->cpu_rdev);  in tegra30_regulator_prepare_suspend()
381 	err = regulator_sync_voltage_rdev(tegra->core_rdev);  in tegra30_regulator_prepare_suspend()
422 	if (!tegra->core_rdev || !tegra->cpu_rdev)  in tegra30_regulator_prepare_reboot()
425 	WRITE_ONCE(tegra->sys_reboot_mode_req, true);  in tegra30_regulator_prepare_reboot()
428 	 * Some devices use CPU soft-reboot method and in this case we  in tegra30_regulator_prepare_reboot()
432 	err = regulator_sync_voltage_rdev(tegra->cpu_rdev);  in tegra30_regulator_prepare_reboot()
436 	err = regulator_sync_voltage_rdev(tegra->core_rdev);  in tegra30_regulator_prepare_reboot()
440 	WRITE_ONCE(tegra->sys_reboot_mode_req, sys_reboot_mode);  in tegra30_regulator_prepare_reboot()
466 	struct device_node *np = rdev->dev.of_node;  in tegra30_regulator_attach()
468 	if (of_property_read_bool(np, "nvidia,tegra-core-regulator") &&  in tegra30_regulator_attach()
469 	    !tegra->core_rdev) {  in tegra30_regulator_attach()
470 		tegra->core_rdev = rdev;  in tegra30_regulator_attach()
474 	if (of_property_read_bool(np, "nvidia,tegra-cpu-regulator") &&  in tegra30_regulator_attach()
475 	    !tegra->cpu_rdev) {  in tegra30_regulator_attach()
476 		tegra->cpu_rdev = rdev;  in tegra30_regulator_attach()
480 	return -EINVAL;  in tegra30_regulator_attach()
494 		return -EPERM;  in tegra30_regulator_detach()
496 	if (tegra->core_rdev == rdev) {  in tegra30_regulator_detach()
497 		tegra->core_rdev = NULL;  in tegra30_regulator_detach()
501 	if (tegra->cpu_rdev == rdev) {  in tegra30_regulator_detach()
502 		tegra->cpu_rdev = NULL;  in tegra30_regulator_detach()
506 	return -EINVAL;  in tegra30_regulator_detach()
523 	if (!of_machine_is_compatible("nvidia,tegra30"))  in tegra_regulator_coupler_init()