soc/qcom/spm.c

29 #define SPM_CTL_INDEX		0x7f
31 #define SPM_CTL_EN		BIT(0)
34 #define SPM_VCTL_VLVL			GENMASK(7, 0)
35 #define SPM_PMIC_DATA_0_VLVL		GENMASK(7, 0)
36 #define SPM_PMIC_DATA_1_MIN_VSEL	GENMASK(5, 0)
91 	[SPM_REG_AVS_CTL]	= 0x904,
92 	[SPM_REG_AVS_LIMIT]	= 0x908,
97 	.avs_ctl = 0x1010031,
98 	.avs_limit = 0x4580458,
103 	.avs_ctl = 0x101c031,
104 	.avs_limit = 0x4580458,
109 	.avs_ctl = 0x1010031,
110 	.avs_limit = 0x4700470,
115 	.avs_ctl = 0x1010031,
116 	.avs_limit = 0x4200420,
120 	[SPM_REG_CFG]		= 0x08,
121 	[SPM_REG_SPM_CTL]	= 0x30,
122 	[SPM_REG_DLY]		= 0x34,
123 	[SPM_REG_SEQ_ENTRY]	= 0x400,
129 	.spm_cfg = 0x1,
130 	.spm_dly = 0x3C102800,
131 	.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
132 		0x5B, 0x60, 0x03, 0x60, 0x76, 0x76, 0x0B, 0x94, 0x5B, 0x80,
133 		0x10, 0x26, 0x30, 0x0F },
134 	.start_index[PM_SLEEP_MODE_STBY] = 0,
141 	.spm_cfg = 0x1,
142 	.spm_dly = 0x3C102800,
143 	.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
144 		0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
145 		0x80, 0x10, 0x26, 0x30, 0x0F },
146 	.start_index[PM_SLEEP_MODE_STBY] = 0,
152 	.spm_cfg = 0x1,
153 	.spm_dly = 0x3C102800,
154 	.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x50, 0x1B, 0x10, 0x80,
155 		0x30, 0x90, 0x5B, 0x60, 0x50, 0x03, 0x60, 0x76, 0x76, 0x0B,
156 		0x50, 0x1B, 0x94, 0x5B, 0x80, 0x10, 0x26, 0x30, 0x50, 0x0F },
157 	.start_index[PM_SLEEP_MODE_STBY] = 0,
162 	[SPM_REG_CFG]		= 0x08,
163 	[SPM_REG_SPM_CTL]	= 0x30,
164 	[SPM_REG_DLY]		= 0x34,
165 	[SPM_REG_PMIC_DATA_0]	= 0x40,
166 	[SPM_REG_PMIC_DATA_1]	= 0x44,
172 	.spm_cfg = 0x14,
173 	.spm_dly = 0x3c11840a,
174 	.pmic_data[0] = 0x03030080,
175 	.pmic_data[1] = 0x00030000,
176 	.start_index[PM_SLEEP_MODE_STBY] = 0,
182 	.spm_cfg = 0x14,
183 	.spm_dly = 0x3c102800,
184 	.pmic_data[0] = 0x03030080,
185 	.pmic_data[1] = 0x00030000,
186 	.start_index[PM_SLEEP_MODE_STBY] = 0,
191 	[SPM_REG_CFG]		= 0x08,
192 	[SPM_REG_SPM_CTL]	= 0x30,
193 	[SPM_REG_DLY]		= 0x34,
194 	[SPM_REG_SEQ_ENTRY]	= 0x80,
200 	.spm_cfg = 0x1,
201 	.spm_dly = 0x3C102800,
202 	.seq = { 0x03, 0x0B, 0x0F, 0x00, 0x20, 0x80, 0x10, 0xE8, 0x5B, 0x03,
203 		0x3B, 0xE8, 0x5B, 0x82, 0x10, 0x0B, 0x30, 0x06, 0x26, 0x30,
204 		0x0F },
205 	.start_index[PM_SLEEP_MODE_STBY] = 0,
212 	.spm_cfg = 0x0,
213 	.spm_dly = 0x3C102800,
214 	.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
215 		0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
216 		0x80, 0x10, 0x26, 0x30, 0x0F },
217 	.start_index[PM_SLEEP_MODE_STBY] = 0,
222 	[SPM_REG_CFG]		= 0x08,
223 	[SPM_REG_STS0]		= 0x0c,
224 	[SPM_REG_STS1]		= 0x10,
225 	[SPM_REG_VCTL]		= 0x14,
226 	[SPM_REG_AVS_CTL]	= 0x18,
227 	[SPM_REG_SPM_CTL]	= 0x20,
228 	[SPM_REG_PMIC_DLY]	= 0x24,
229 	[SPM_REG_PMIC_DATA_0]	= 0x28,
230 	[SPM_REG_PMIC_DATA_1]	= 0x2C,
231 	[SPM_REG_SEQ_ENTRY]	= 0x80,
238 	REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500);
242 	.spm_cfg = 0x1F,
243 	.pmic_dly = 0x02020004,
244 	.pmic_data[0] = 0x0084009C,
245 	.pmic_data[1] = 0x00A4001C,
246 	.seq = { 0x03, 0x0F, 0x00, 0x24, 0x54, 0x10, 0x09, 0x03, 0x01,
247 		0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F },
248 	.start_index[PM_SLEEP_MODE_STBY] = 0,
337 	vlevel = volt_sel | 0x80; /* band */  in smp_set_vdd_v1_1()
400 		saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);  in spm_get_cpu()
426 		return 0;  in spm_register_regulator()
444 	if (ret < 0)  in spm_register_regulator()
474 	return 0;  in spm_register_regulator()
484 	{ .compatible = "qcom,msm8909-saw2-v3.0-cpu",
486 	{ .compatible = "qcom,msm8916-saw2-v3.0-cpu",
488 	{ .compatible = "qcom,msm8939-saw2-v3.0-cpu",
518 	drv->reg_base = devm_platform_ioremap_resource(pdev, 0);  in spm_dev_probe()
547 				drv->reg_data->pmic_data[0]);  in spm_dev_probe()
558 	return 0;  in spm_dev_probe()