Lines Matching +full:0 +full:x0a0

6 #define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
7 #define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
8 #define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
9 #define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
10 #define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
11 #define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
12 #define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
13 #define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN		0x08c
14 #define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN		0x0a0
15 #define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN		0x0a4
16 #define MT8173_DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
17 #define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x0b0
18 #define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
19 #define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN	0x0bc
21 #define MT8173_AAL_SEL_IN_MERGE				BIT(0)
22 #define MT8173_COLOR0_SEL_IN_OVL0			BIT(0)
23 #define MT8173_COLOR0_SOUT_MERGE			BIT(0)
24 #define MT8173_DPI0_SEL_IN_MASK				GENMASK(1, 0)
25 #define MT8173_DPI0_SEL_IN_RDMA1			BIT(0)
26 #define MT8173_DSI0_SEL_IN_UFOE				BIT(0)
27 #define MT8173_GAMMA_MOUT_EN_RDMA1			BIT(0)
28 #define MT8173_OD0_MOUT_EN_RDMA0			BIT(0)
29 #define MT8173_OVL0_MOUT_EN_COLOR0			BIT(0)
30 #define MT8173_OVL1_MOUT_EN_COLOR1			BIT(0)
31 #define MT8173_UFOE_MOUT_EN_DSI0			BIT(0)
32 #define MT8173_UFOE_SEL_IN_RDMA0			BIT(0)
33 #define MT8173_RDMA0_SOUT_COLOR0			BIT(0)
51 		MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
55 		MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
63 		MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
67 		MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
71 		MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */