Lines Matching +full:clock +full:- +full:source
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * QE UCC API Set - UCC specific routines implementations.
33 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_mii_mng()
34 return -EINVAL; in ucc_set_qe_mux_mii_mng()
37 qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, in ucc_set_qe_mux_mii_mng()
50 * 'ucc_num' is the UCC number, from 0 - 7.
62 case 0: guemr = &qe_immr->ucc1.slow.guemr; in ucc_set_type()
64 case 1: guemr = &qe_immr->ucc2.slow.guemr; in ucc_set_type()
66 case 2: guemr = &qe_immr->ucc3.slow.guemr; in ucc_set_type()
68 case 3: guemr = &qe_immr->ucc4.slow.guemr; in ucc_set_type()
70 case 4: guemr = &qe_immr->ucc5.slow.guemr; in ucc_set_type()
72 case 5: guemr = &qe_immr->ucc6.slow.guemr; in ucc_set_type()
74 case 6: guemr = &qe_immr->ucc7.slow.guemr; in ucc_set_type()
76 case 7: guemr = &qe_immr->ucc8.slow.guemr; in ucc_set_type()
79 return -EINVAL; in ucc_set_type()
94 *cmxucr = &qe_immr->qmx.cmxucr[cmx]; in get_cmxucr_reg()
95 *shift = 16 - 8 * (ucc_num & 2); in get_cmxucr_reg()
105 if (ucc_num > UCC_MAX_NUM - 1) in ucc_mux_set_grant_tsa_bkpt()
106 return -EINVAL; in ucc_mux_set_grant_tsa_bkpt()
119 int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, in ucc_set_qe_mux_rxtx() argument
128 if (ucc_num > UCC_MAX_NUM - 1) in ucc_set_qe_mux_rxtx()
129 return -EINVAL; in ucc_set_qe_mux_rxtx()
133 return -EINVAL; in ucc_set_qe_mux_rxtx()
139 switch (clock) { in ucc_set_qe_mux_rxtx()
154 switch (clock) { in ucc_set_qe_mux_rxtx()
169 switch (clock) { in ucc_set_qe_mux_rxtx()
185 switch (clock) { in ucc_set_qe_mux_rxtx()
203 /* Check for invalid combination of clock and UCC number */ in ucc_set_qe_mux_rxtx()
205 return -ENOENT; in ucc_set_qe_mux_rxtx()
216 static int ucc_get_tdm_common_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_common_clk() argument
218 int clock_bits = -EINVAL; in ucc_get_tdm_common_clk()
222 * clock source BRG3,4 and CLK1,2 in ucc_get_tdm_common_clk()
224 * clock source BRG12,13 and CLK23,24 in ucc_get_tdm_common_clk()
231 switch (clock) { in ucc_get_tdm_common_clk()
252 switch (clock) { in ucc_get_tdm_common_clk()
276 static int ucc_get_tdm_rx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_rx_clk() argument
278 int clock_bits = -EINVAL; in ucc_get_tdm_rx_clk()
282 switch (clock) { in ucc_get_tdm_rx_clk()
294 switch (clock) { in ucc_get_tdm_rx_clk()
306 switch (clock) { in ucc_get_tdm_rx_clk()
318 switch (clock) { in ucc_get_tdm_rx_clk()
330 switch (clock) { in ucc_get_tdm_rx_clk()
342 switch (clock) { in ucc_get_tdm_rx_clk()
354 switch (clock) { in ucc_get_tdm_rx_clk()
366 switch (clock) { in ucc_get_tdm_rx_clk()
382 static int ucc_get_tdm_tx_clk(u32 tdm_num, enum qe_clock clock) in ucc_get_tdm_tx_clk() argument
384 int clock_bits = -EINVAL; in ucc_get_tdm_tx_clk()
388 switch (clock) { in ucc_get_tdm_tx_clk()
400 switch (clock) { in ucc_get_tdm_tx_clk()
412 switch (clock) { in ucc_get_tdm_tx_clk()
424 switch (clock) { in ucc_get_tdm_tx_clk()
436 switch (clock) { in ucc_get_tdm_tx_clk()
448 switch (clock) { in ucc_get_tdm_tx_clk()
460 switch (clock) { in ucc_get_tdm_tx_clk()
472 switch (clock) { in ucc_get_tdm_tx_clk()
488 /* tdm_num: TDM A-H port num is 0-7 */
490 enum qe_clock clock) in ucc_get_tdm_rxtx_clk() argument
494 clock_bits = ucc_get_tdm_common_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
498 clock_bits = ucc_get_tdm_rx_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
500 clock_bits = ucc_get_tdm_tx_clk(tdm_num, clock); in ucc_get_tdm_rxtx_clk()
510 shift -= tdm_num * 4; in ucc_get_tdm_clk_shift()
512 shift -= (tdm_num - 4) * 4; in ucc_get_tdm_clk_shift()
517 int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock, in ucc_set_tdm_rxtx_clk() argument
525 qe_mux_reg = &qe_immr->qmx; in ucc_set_tdm_rxtx_clk()
528 return -EINVAL; in ucc_set_tdm_rxtx_clk()
532 return -EINVAL; in ucc_set_tdm_rxtx_clk()
534 clock_bits = ucc_get_tdm_rxtx_clk(mode, tdm_num, clock); in ucc_set_tdm_rxtx_clk()
536 return -EINVAL; in ucc_set_tdm_rxtx_clk()
540 cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l : in ucc_set_tdm_rxtx_clk()
541 &qe_mux_reg->cmxsi1cr_h; in ucc_set_tdm_rxtx_clk()
549 static int ucc_get_tdm_sync_source(u32 tdm_num, enum qe_clock clock, in ucc_get_tdm_sync_source() argument
552 int source = -EINVAL; in ucc_get_tdm_sync_source() local
554 if (mode == COMM_DIR_RX && clock == QE_RSYNC_PIN) { in ucc_get_tdm_sync_source()
555 source = 0; in ucc_get_tdm_sync_source()
556 return source; in ucc_get_tdm_sync_source()
558 if (mode == COMM_DIR_TX && clock == QE_TSYNC_PIN) { in ucc_get_tdm_sync_source()
559 source = 0; in ucc_get_tdm_sync_source()
560 return source; in ucc_get_tdm_sync_source()
566 switch (clock) { in ucc_get_tdm_sync_source()
568 source = 1; in ucc_get_tdm_sync_source()
571 source = 2; in ucc_get_tdm_sync_source()
579 switch (clock) { in ucc_get_tdm_sync_source()
581 source = 1; in ucc_get_tdm_sync_source()
584 source = 2; in ucc_get_tdm_sync_source()
592 switch (clock) { in ucc_get_tdm_sync_source()
594 source = 1; in ucc_get_tdm_sync_source()
597 source = 2; in ucc_get_tdm_sync_source()
605 switch (clock) { in ucc_get_tdm_sync_source()
607 source = 1; in ucc_get_tdm_sync_source()
610 source = 2; in ucc_get_tdm_sync_source()
618 return source; in ucc_get_tdm_sync_source()
626 shift -= tdm_num * 2; in ucc_get_tdm_sync_shift()
631 int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock, in ucc_set_tdm_rxtx_sync() argument
634 int source; in ucc_set_tdm_rxtx_sync() local
638 qe_mux_reg = &qe_immr->qmx; in ucc_set_tdm_rxtx_sync()
641 return -EINVAL; in ucc_set_tdm_rxtx_sync()
645 return -EINVAL; in ucc_set_tdm_rxtx_sync()
647 source = ucc_get_tdm_sync_source(tdm_num, clock, mode); in ucc_set_tdm_rxtx_sync()
648 if (source < 0) in ucc_set_tdm_rxtx_sync()
649 return -EINVAL; in ucc_set_tdm_rxtx_sync()
653 qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr, in ucc_set_tdm_rxtx_sync()
655 source << shift); in ucc_set_tdm_rxtx_sync()