Lines Matching +full:vpu +full:- +full:side
1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/reset-controller.h>
54 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_reset()
55 val = readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
56 writel_relaxed(val & ~BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
57 writel_relaxed(val | BIT(id), pmu->pmc_base + PMC_SW_RST); in pmu_reset_reset()
58 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_reset()
69 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_assert()
70 val &= readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_assert()
71 writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); in pmu_reset_assert()
72 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_assert()
83 spin_lock_irqsave(&pmu->lock, flags); in pmu_reset_deassert()
84 val |= readl_relaxed(pmu->pmc_base + PMC_SW_RST); in pmu_reset_deassert()
85 writel_relaxed(val, pmu->pmc_base + PMC_SW_RST); in pmu_reset_deassert()
86 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_reset_deassert()
107 pmu->reset = pmu_reset; in pmu_reset_init()
108 pmu->reset.of_node = pmu->of_node; in pmu_reset_init()
110 ret = reset_controller_register(&pmu->reset); in pmu_reset_init()
139 * unfortunate side-effect - they cause memory already read into registers
140 * for the if () to be re-read for the bit-set or bit-clear operation.
146 struct pmu_data *pmu = pmu_dom->pmu; in pmu_domain_power_off()
149 void __iomem *pmu_base = pmu->pmu_base; in pmu_domain_power_off()
150 void __iomem *pmc_base = pmu->pmc_base; in pmu_domain_power_off()
152 spin_lock_irqsave(&pmu->lock, flags); in pmu_domain_power_off()
155 if (pmu_dom->iso_mask) { in pmu_domain_power_off()
156 val = ~pmu_dom->iso_mask; in pmu_domain_power_off()
162 if (pmu_dom->rst_mask) { in pmu_domain_power_off()
163 val = ~pmu_dom->rst_mask; in pmu_domain_power_off()
169 val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask; in pmu_domain_power_off()
172 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_domain_power_off()
180 struct pmu_data *pmu = pmu_dom->pmu; in pmu_domain_power_on()
183 void __iomem *pmu_base = pmu->pmu_base; in pmu_domain_power_on()
184 void __iomem *pmc_base = pmu->pmc_base; in pmu_domain_power_on()
186 spin_lock_irqsave(&pmu->lock, flags); in pmu_domain_power_on()
189 val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR); in pmu_domain_power_on()
193 if (pmu_dom->rst_mask) { in pmu_domain_power_on()
194 val = pmu_dom->rst_mask; in pmu_domain_power_on()
200 if (pmu_dom->iso_mask) { in pmu_domain_power_on()
201 val = pmu_dom->iso_mask; in pmu_domain_power_on()
206 spin_unlock_irqrestore(&pmu->lock, flags); in pmu_domain_power_on()
214 unsigned int val = readl_relaxed(domain->pmu->pmu_base + PMU_PWR); in __pmu_domain_register()
216 domain->base.power_off = pmu_domain_power_off; in __pmu_domain_register()
217 domain->base.power_on = pmu_domain_power_on; in __pmu_domain_register()
219 pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask)); in __pmu_domain_register()
222 of_genpd_add_provider_simple(np, &domain->base); in __pmu_domain_register()
229 struct irq_chip_generic *gc = pmu->irq_gc; in pmu_irq_handler()
230 struct irq_domain *domain = pmu->irq_domain; in pmu_irq_handler()
231 void __iomem *base = gc->reg_base; in pmu_irq_handler()
232 u32 stat = readl_relaxed(base + PMC_IRQ_CAUSE) & gc->mask_cache; in pmu_irq_handler()
241 u32 hwirq = fls(stat) - 1; in pmu_irq_handler()
274 writel(0, pmu->pmc_base + PMC_IRQ_MASK); in dove_init_pmu_irq()
275 writel(0, pmu->pmc_base + PMC_IRQ_CAUSE); in dove_init_pmu_irq()
277 domain = irq_domain_add_linear(pmu->of_node, NR_PMU_IRQS, in dove_init_pmu_irq()
281 return -ENOMEM; in dove_init_pmu_irq()
295 gc->reg_base = pmu->pmc_base; in dove_init_pmu_irq()
296 gc->chip_types[0].regs.mask = PMC_IRQ_MASK; in dove_init_pmu_irq()
297 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in dove_init_pmu_irq()
298 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in dove_init_pmu_irq()
300 pmu->irq_domain = domain; in dove_init_pmu_irq()
301 pmu->irq_gc = gc; in dove_init_pmu_irq()
317 return -ENOMEM; in dove_init_pmu_legacy()
319 spin_lock_init(&pmu->lock); in dove_init_pmu_legacy()
320 pmu->pmc_base = initdata->pmc_base; in dove_init_pmu_legacy()
321 pmu->pmu_base = initdata->pmu_base; in dove_init_pmu_legacy()
324 for (domain_initdata = initdata->domains; domain_initdata->name; in dove_init_pmu_legacy()
330 domain->pmu = pmu; in dove_init_pmu_legacy()
331 domain->pwr_mask = domain_initdata->pwr_mask; in dove_init_pmu_legacy()
332 domain->rst_mask = domain_initdata->rst_mask; in dove_init_pmu_legacy()
333 domain->iso_mask = domain_initdata->iso_mask; in dove_init_pmu_legacy()
334 domain->base.name = domain_initdata->name; in dove_init_pmu_legacy()
340 ret = dove_init_pmu_irq(pmu, initdata->irq); in dove_init_pmu_legacy()
344 if (pmu->irq_domain) in dove_init_pmu_legacy()
345 irq_domain_associate_many(pmu->irq_domain, in dove_init_pmu_legacy()
346 initdata->irq_domain_start, in dove_init_pmu_legacy()
353 * pmu: power-manager@d0000 {
354 * compatible = "marvell,dove-pmu";
357 * interrupt-controller;
358 * #reset-cells = 1;
359 * vpu_domain: vpu-domain {
360 * #power-domain-cells = <0>;
365 * gpu_domain: gpu-domain {
366 * #power-domain-cells = <0>;
380 np_pmu = of_find_compatible_node(NULL, NULL, "marvell,dove-pmu"); in dove_init_pmu()
386 pr_err("%pOFn: failed to find domains sub-node\n", np_pmu); in dove_init_pmu()
392 return -ENOMEM; in dove_init_pmu()
394 spin_lock_init(&pmu->lock); in dove_init_pmu()
395 pmu->of_node = np_pmu; in dove_init_pmu()
396 pmu->pmc_base = of_iomap(pmu->of_node, 0); in dove_init_pmu()
397 pmu->pmu_base = of_iomap(pmu->of_node, 1); in dove_init_pmu()
398 if (!pmu->pmc_base || !pmu->pmu_base) { in dove_init_pmu()
400 iounmap(pmu->pmu_base); in dove_init_pmu()
401 iounmap(pmu->pmc_base); in dove_init_pmu()
403 return -ENOMEM; in dove_init_pmu()
418 domain->pmu = pmu; in dove_init_pmu()
419 domain->base.name = kasprintf(GFP_KERNEL, "%pOFn", np); in dove_init_pmu()
420 if (!domain->base.name) { in dove_init_pmu()
427 &domain->pwr_mask); in dove_init_pmu()
429 &domain->iso_mask); in dove_init_pmu()
436 ret = of_parse_phandle_with_args(np, "resets", "#reset-cells", in dove_init_pmu()
439 if (args.np == pmu->of_node) in dove_init_pmu()
440 domain->rst_mask = BIT(args.args[0]); in dove_init_pmu()
448 parent_irq = irq_of_parse_and_map(pmu->of_node, 0); in dove_init_pmu()