1 // SPDX-License-Identifier: GPL-2.0-only
3  * MIPS-specific support for Broadcom STB S2/S3/S5 power management
5  * Copyright (C) 2016-2017 Broadcom
94 	ctx->cp0_regs[CONTEXT] = read_c0_context();  in brcm_pm_save_cp0_context()
95 	ctx->cp0_regs[USER_LOCAL] = read_c0_userlocal();  in brcm_pm_save_cp0_context()
96 	ctx->cp0_regs[PGMK] = read_c0_pagemask();  in brcm_pm_save_cp0_context()
97 	ctx->cp0_regs[HWRENA] = read_c0_cache();  in brcm_pm_save_cp0_context()
98 	ctx->cp0_regs[COMPARE] = read_c0_compare();  in brcm_pm_save_cp0_context()
99 	ctx->cp0_regs[STATUS] = read_c0_status();  in brcm_pm_save_cp0_context()
102 	ctx->cp0_regs[CONFIG] = read_c0_brcm_config();  in brcm_pm_save_cp0_context()
103 	ctx->cp0_regs[MODE] = read_c0_brcm_mode();  in brcm_pm_save_cp0_context()
104 	ctx->cp0_regs[EDSP] = read_c0_brcm_edsp();  in brcm_pm_save_cp0_context()
105 	ctx->cp0_regs[BOOT_VEC] = read_c0_brcm_bootvec();  in brcm_pm_save_cp0_context()
106 	ctx->cp0_regs[EBASE] = read_c0_ebase();  in brcm_pm_save_cp0_context()
108 	ctx->sc_boot_vec = bmips_read_zscm_reg(0xa0);  in brcm_pm_save_cp0_context()
114 	bmips_write_zscm_reg(0xa0, ctx->sc_boot_vec);  in brcm_pm_restore_cp0_context()
117 	write_c0_context(ctx->cp0_regs[CONTEXT]);  in brcm_pm_restore_cp0_context()
118 	write_c0_userlocal(ctx->cp0_regs[USER_LOCAL]);  in brcm_pm_restore_cp0_context()
119 	write_c0_pagemask(ctx->cp0_regs[PGMK]);  in brcm_pm_restore_cp0_context()
120 	write_c0_cache(ctx->cp0_regs[HWRENA]);  in brcm_pm_restore_cp0_context()
121 	write_c0_compare(ctx->cp0_regs[COMPARE]);  in brcm_pm_restore_cp0_context()
122 	write_c0_status(ctx->cp0_regs[STATUS]);  in brcm_pm_restore_cp0_context()
125 	write_c0_brcm_config(ctx->cp0_regs[CONFIG]);  in brcm_pm_restore_cp0_context()
126 	write_c0_brcm_mode(ctx->cp0_regs[MODE]);  in brcm_pm_restore_cp0_context()
127 	write_c0_brcm_edsp(ctx->cp0_regs[EDSP]);  in brcm_pm_restore_cp0_context()
128 	write_c0_brcm_bootvec(ctx->cp0_regs[BOOT_VEC]);  in brcm_pm_restore_cp0_context()
129 	write_c0_ebase(ctx->cp0_regs[EBASE]);  in brcm_pm_restore_cp0_context()
160 	/* Clear magic s3 warm-boot value */  in brcmstb_pm_s5()
260 	 * 3: I-Cache line size  in brcmstb_pm_s2()
272 	s2_params[5] = (u32)(bmips_smp_int_vec_end -  in brcmstb_pm_s2()
307 	int ret = -EINVAL;  in brcmstb_pm_enter()
339 	{ .compatible = "brcm,brcmstb-aon-ctrl" },
344 	{ .compatible = "brcm,brcmstb-ddr-phy" },
349 	{ .compatible = "brcm,brcmstb-memc-arb" },
354 	{ .compatible = "brcm,brcmstb-timers" },
361 	return of_io_request_and_map(dn, index, dn->full_name);  in brcmstb_ioremap_node()
372 		return ERR_PTR(-EINVAL);  in brcmstb_ioremap_match()
375 		*ofdata = match->data;  in brcmstb_ioremap_match()
403 	/* Map MEMC DDR PHY registers */  in brcmstb_pm_init()
421 	/* MEMC ARB registers */  in brcmstb_pm_init()
424 		pr_err("error mapping MEMC ARB\n");  in brcmstb_pm_init()