Lines Matching +full:dma +full:- +full:write

1 // SPDX-License-Identifier: GPL-2.0
3 * ESP front-end for Amiga ZORRO SCSI systems.
11 * Blizzard 1230 DMA and probe function fixes
24 * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
32 #include <linux/dma-mapping.h>
55 /* per-board register layout definitions */
57 /* Blizzard 1230 DMA interface */
60 unsigned char dma_addr; /* DMA address [0x0000] */
62 unsigned char dma_latch; /* DMA latch [0x8000] */
65 /* Blizzard 1230II DMA interface */
68 unsigned char dma_addr; /* DMA address [0x0000] */
70 unsigned char dma_latch; /* DMA latch [0x0010] */
73 /* Blizzard 2060 DMA interface */
76 unsigned char dma_led_ctrl; /* DMA led control [0x000] */
78 unsigned char dma_addr0; /* DMA address (MSB) [0x010] */
80 unsigned char dma_addr1; /* DMA address [0x014] */
82 unsigned char dma_addr2; /* DMA address [0x018] */
84 unsigned char dma_addr3; /* DMA address (LSB) [0x01c] */
87 /* DMA control bits */
90 /* Cyberstorm DMA interface */
93 unsigned char dma_addr0; /* DMA address (MSB) [0x000] */
95 unsigned char dma_addr1; /* DMA address [0x002] */
97 unsigned char dma_addr2; /* DMA address [0x004] */
99 unsigned char dma_addr3; /* DMA address (LSB) [0x006] */
101 unsigned char cond_reg; /* DMA cond (ro) [0x402] */
102 #define ctrl_reg cond_reg /* DMA control (wo) [0x402] */
105 /* DMA control bits */
106 #define CYBER_DMA_WRITE 0x40 /* DMA direction. 1 = write */
107 #define CYBER_DMA_Z3 0x20 /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */
109 /* DMA status bits */
110 #define CYBER_DMA_HNDL_INTR 0x80 /* DMA IRQ pending? */
112 /* The CyberStorm II DMA interface */
114 unsigned char cond_reg; /* DMA cond (ro) [0x000] */
115 #define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
117 unsigned char dma_addr0; /* DMA address (MSB) [0x040] */
119 unsigned char dma_addr1; /* DMA address [0x044] */
121 unsigned char dma_addr2; /* DMA address [0x048] */
123 unsigned char dma_addr3; /* DMA address (LSB) [0x04c] */
126 /* Fastlane DMA interface */
129 unsigned char cond_reg; /* DMA status (ro) [0x0000] */
130 #define ctrl_reg cond_reg /* DMA control (wo) [0x0000] */
132 unsigned char clear_strobe; /* DMA clear (wo) [0x0040] */
141 /* DMA status bits */
146 /* DMA control bits */
149 #define FASTLANE_DMA_WRITE 0x08 /* 1 = write */
150 #define FASTLANE_DMA_ENABLE 0x04 /* Enable DMA */
151 #define FASTLANE_DMA_EDI 0x02 /* Enable DMA IRQ ? */
158 struct esp *esp; /* our ESP instance - for Scsi_host* */
167 * On Oktagon, it is one byte - use a different accessor there.
169 * Oktagon needs PDMA - currently unsupported!
174 writeb(val, esp->regs + (reg * 4UL)); in zorro_esp_write8()
179 return readb(esp->regs + (reg * 4UL)); in zorro_esp_read8()
184 /* check ESP status register; DMA has no status reg. */ in zorro_esp_irq_pending()
193 struct cyber_dma_registers __iomem *dregs = esp->dma_regs; in cyber_esp_irq_pending()
194 unsigned char dma_status = readb(&dregs->cond_reg); in cyber_esp_irq_pending()
196 /* It's important to check the DMA IRQ bit in the correct way! */ in cyber_esp_irq_pending()
203 struct fastlane_dma_registers __iomem *dregs = esp->dma_regs; in fastlane_esp_irq_pending()
206 dma_status = readb(&dregs->cond_reg); in fastlane_esp_irq_pending()
211 /* Return non-zero if ESP requested IRQ */ in fastlane_esp_irq_pending()
248 struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev); in fastlane_esp_dma_invalidate()
249 struct fastlane_dma_registers __iomem *dregs = esp->dma_regs; in fastlane_esp_dma_invalidate()
250 unsigned char *ctrl_data = &zep->ctrl_data; in fastlane_esp_dma_invalidate()
253 writeb(0, &dregs->clear_strobe); in fastlane_esp_dma_invalidate()
254 z_writel(0, zep->board_base); in fastlane_esp_dma_invalidate()
257 /* Blizzard 1230/60 SCSI-IV DMA */
260 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_blz1230_dma_cmd() argument
262 struct blz1230_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_blz1230_dma_cmd()
263 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_blz1230_dma_cmd()
266 * Use PIO if transferring message bytes to esp->command_block_dma. in zorro_esp_send_blz1230_dma_cmd()
267 * PIO requires a virtual address, so substitute esp->command_block in zorro_esp_send_blz1230_dma_cmd()
270 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_blz1230_dma_cmd()
271 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_blz1230_dma_cmd()
272 dma_count, write, cmd); in zorro_esp_send_blz1230_dma_cmd()
276 /* Clear the results of a possible prior esp->ops->send_dma_cmd() */ in zorro_esp_send_blz1230_dma_cmd()
277 esp->send_cmd_error = 0; in zorro_esp_send_blz1230_dma_cmd()
278 esp->send_cmd_residual = 0; in zorro_esp_send_blz1230_dma_cmd()
280 if (write) in zorro_esp_send_blz1230_dma_cmd()
281 /* DMA receive */ in zorro_esp_send_blz1230_dma_cmd()
282 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz1230_dma_cmd()
285 /* DMA send */ in zorro_esp_send_blz1230_dma_cmd()
286 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz1230_dma_cmd()
290 if (write) in zorro_esp_send_blz1230_dma_cmd()
295 writeb((addr >> 24) & 0xff, &dregs->dma_latch); in zorro_esp_send_blz1230_dma_cmd()
296 writeb((addr >> 24) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
297 writeb((addr >> 16) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
298 writeb((addr >> 8) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
299 writeb(addr & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230_dma_cmd()
308 /* Blizzard 1230-II DMA */
311 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_blz1230II_dma_cmd() argument
313 struct blz1230II_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_blz1230II_dma_cmd()
314 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_blz1230II_dma_cmd()
316 /* Use PIO if transferring message bytes to esp->command_block_dma */ in zorro_esp_send_blz1230II_dma_cmd()
317 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_blz1230II_dma_cmd()
318 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_blz1230II_dma_cmd()
319 dma_count, write, cmd); in zorro_esp_send_blz1230II_dma_cmd()
323 esp->send_cmd_error = 0; in zorro_esp_send_blz1230II_dma_cmd()
324 esp->send_cmd_residual = 0; in zorro_esp_send_blz1230II_dma_cmd()
326 if (write) in zorro_esp_send_blz1230II_dma_cmd()
327 /* DMA receive */ in zorro_esp_send_blz1230II_dma_cmd()
328 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz1230II_dma_cmd()
331 /* DMA send */ in zorro_esp_send_blz1230II_dma_cmd()
332 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz1230II_dma_cmd()
336 if (write) in zorro_esp_send_blz1230II_dma_cmd()
341 writeb((addr >> 24) & 0xff, &dregs->dma_latch); in zorro_esp_send_blz1230II_dma_cmd()
342 writeb((addr >> 16) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
343 writeb((addr >> 8) & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
344 writeb(addr & 0xff, &dregs->dma_addr); in zorro_esp_send_blz1230II_dma_cmd()
353 /* Blizzard 2060 DMA */
356 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_blz2060_dma_cmd() argument
358 struct blz2060_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_blz2060_dma_cmd()
359 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_blz2060_dma_cmd()
361 /* Use PIO if transferring message bytes to esp->command_block_dma */ in zorro_esp_send_blz2060_dma_cmd()
362 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_blz2060_dma_cmd()
363 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_blz2060_dma_cmd()
364 dma_count, write, cmd); in zorro_esp_send_blz2060_dma_cmd()
368 esp->send_cmd_error = 0; in zorro_esp_send_blz2060_dma_cmd()
369 esp->send_cmd_residual = 0; in zorro_esp_send_blz2060_dma_cmd()
371 if (write) in zorro_esp_send_blz2060_dma_cmd()
372 /* DMA receive */ in zorro_esp_send_blz2060_dma_cmd()
373 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz2060_dma_cmd()
376 /* DMA send */ in zorro_esp_send_blz2060_dma_cmd()
377 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_blz2060_dma_cmd()
381 if (write) in zorro_esp_send_blz2060_dma_cmd()
386 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_blz2060_dma_cmd()
387 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_blz2060_dma_cmd()
388 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_blz2060_dma_cmd()
389 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_blz2060_dma_cmd()
398 /* Cyberstorm I DMA */
401 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_cyber_dma_cmd() argument
403 struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev); in zorro_esp_send_cyber_dma_cmd()
404 struct cyber_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_cyber_dma_cmd()
405 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_cyber_dma_cmd()
406 unsigned char *ctrl_data = &zep->ctrl_data; in zorro_esp_send_cyber_dma_cmd()
408 /* Use PIO if transferring message bytes to esp->command_block_dma */ in zorro_esp_send_cyber_dma_cmd()
409 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_cyber_dma_cmd()
410 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_cyber_dma_cmd()
411 dma_count, write, cmd); in zorro_esp_send_cyber_dma_cmd()
415 esp->send_cmd_error = 0; in zorro_esp_send_cyber_dma_cmd()
416 esp->send_cmd_residual = 0; in zorro_esp_send_cyber_dma_cmd()
421 if (write) { in zorro_esp_send_cyber_dma_cmd()
422 /* DMA receive */ in zorro_esp_send_cyber_dma_cmd()
423 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_cyber_dma_cmd()
427 /* DMA send */ in zorro_esp_send_cyber_dma_cmd()
428 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_cyber_dma_cmd()
433 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_cyber_dma_cmd()
434 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_cyber_dma_cmd()
435 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_cyber_dma_cmd()
436 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_cyber_dma_cmd()
438 if (write) in zorro_esp_send_cyber_dma_cmd()
443 *ctrl_data &= ~(CYBER_DMA_Z3); /* Z2, do 16 bit DMA */ in zorro_esp_send_cyber_dma_cmd()
445 writeb(*ctrl_data, &dregs->ctrl_reg); in zorro_esp_send_cyber_dma_cmd()
450 /* Cyberstorm II DMA */
453 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_cyberII_dma_cmd() argument
455 struct cyberII_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_cyberII_dma_cmd()
456 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_cyberII_dma_cmd()
458 /* Use PIO if transferring message bytes to esp->command_block_dma */ in zorro_esp_send_cyberII_dma_cmd()
459 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_cyberII_dma_cmd()
460 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_cyberII_dma_cmd()
461 dma_count, write, cmd); in zorro_esp_send_cyberII_dma_cmd()
465 esp->send_cmd_error = 0; in zorro_esp_send_cyberII_dma_cmd()
466 esp->send_cmd_residual = 0; in zorro_esp_send_cyberII_dma_cmd()
471 if (write) { in zorro_esp_send_cyberII_dma_cmd()
472 /* DMA receive */ in zorro_esp_send_cyberII_dma_cmd()
473 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_cyberII_dma_cmd()
477 /* DMA send */ in zorro_esp_send_cyberII_dma_cmd()
478 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_cyberII_dma_cmd()
483 writeb((addr >> 24) & 0xff, &dregs->dma_addr0); in zorro_esp_send_cyberII_dma_cmd()
484 writeb((addr >> 16) & 0xff, &dregs->dma_addr1); in zorro_esp_send_cyberII_dma_cmd()
485 writeb((addr >> 8) & 0xff, &dregs->dma_addr2); in zorro_esp_send_cyberII_dma_cmd()
486 writeb(addr & 0xff, &dregs->dma_addr3); in zorro_esp_send_cyberII_dma_cmd()
491 /* Fastlane DMA */
494 u32 esp_count, u32 dma_count, int write, u8 cmd) in zorro_esp_send_fastlane_dma_cmd() argument
496 struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev); in zorro_esp_send_fastlane_dma_cmd()
497 struct fastlane_dma_registers __iomem *dregs = esp->dma_regs; in zorro_esp_send_fastlane_dma_cmd()
498 u8 phase = esp->sreg & ESP_STAT_PMASK; in zorro_esp_send_fastlane_dma_cmd()
499 unsigned char *ctrl_data = &zep->ctrl_data; in zorro_esp_send_fastlane_dma_cmd()
501 /* Use PIO if transferring message bytes to esp->command_block_dma */ in zorro_esp_send_fastlane_dma_cmd()
502 if (phase == ESP_MIP && addr == esp->command_block_dma) { in zorro_esp_send_fastlane_dma_cmd()
503 esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count, in zorro_esp_send_fastlane_dma_cmd()
504 dma_count, write, cmd); in zorro_esp_send_fastlane_dma_cmd()
508 esp->send_cmd_error = 0; in zorro_esp_send_fastlane_dma_cmd()
509 esp->send_cmd_residual = 0; in zorro_esp_send_fastlane_dma_cmd()
514 if (write) { in zorro_esp_send_fastlane_dma_cmd()
515 /* DMA receive */ in zorro_esp_send_fastlane_dma_cmd()
516 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_fastlane_dma_cmd()
520 /* DMA send */ in zorro_esp_send_fastlane_dma_cmd()
521 dma_sync_single_for_device(esp->dev, addr, esp_count, in zorro_esp_send_fastlane_dma_cmd()
526 writeb(0, &dregs->clear_strobe); in zorro_esp_send_fastlane_dma_cmd()
527 z_writel(addr, ((addr & 0x00ffffff) + zep->board_base)); in zorro_esp_send_fastlane_dma_cmd()
529 if (write) { in zorro_esp_send_fastlane_dma_cmd()
538 writeb(*ctrl_data, &dregs->ctrl_reg); in zorro_esp_send_fastlane_dma_cmd()
545 return esp->send_cmd_error; in zorro_esp_dma_error()
548 /* per-board ESP driver ops */
644 /* per-board config data */
725 zdd = &zorro_esp_boards[ent->driver_data]; in zorro_esp_probe()
727 pr_info("%s found at address 0x%lx.\n", zdd->name, board); in zorro_esp_probe()
732 return -ENOMEM; in zorro_esp_probe()
736 if ((z->rom.er_Type & ERT_TYPEMASK) == ERT_ZORROIII) { in zorro_esp_probe()
738 zep->zorro3 = 1; in zorro_esp_probe()
743 * access to all of memory. Fix up DMA bitmask here. in zorro_esp_probe()
745 z->dev.coherent_dma_mask = DMA_BIT_MASK(32); in zorro_esp_probe()
756 if (zep->zorro3 && ent->driver_data == ZORRO_BLZ1230II) { in zorro_esp_probe()
758 zdd->name, board); in zorro_esp_probe()
762 if (zdd->absolute) { in zorro_esp_probe()
763 ioaddr = zdd->offset; in zorro_esp_probe()
764 dmaaddr = zdd->dma_offset; in zorro_esp_probe()
766 ioaddr = board + zdd->offset; in zorro_esp_probe()
767 dmaaddr = board + zdd->dma_offset; in zorro_esp_probe()
770 if (!zorro_request_device(z, zdd->name)) { in zorro_esp_probe()
773 err = -EBUSY; in zorro_esp_probe()
781 err = -ENOMEM; in zorro_esp_probe()
785 host->base = ioaddr; in zorro_esp_probe()
786 host->this_id = 7; in zorro_esp_probe()
789 esp->host = host; in zorro_esp_probe()
790 esp->dev = &z->dev; in zorro_esp_probe()
792 esp->scsi_id = host->this_id; in zorro_esp_probe()
793 esp->scsi_id_mask = (1 << esp->scsi_id); in zorro_esp_probe()
795 esp->cfreq = 40000000; in zorro_esp_probe()
797 zep->esp = esp; in zorro_esp_probe()
799 dev_set_drvdata(esp->dev, zep); in zorro_esp_probe()
802 if (zep->zorro3 && ent->driver_data == ZORRO_BLZ1230II) { in zorro_esp_probe()
803 /* map full address space up to ESP base for DMA */ in zorro_esp_probe()
804 zep->board_base = ioremap(board, FASTLANE_ESP_ADDR - 1); in zorro_esp_probe()
805 if (!zep->board_base) { in zorro_esp_probe()
807 err = -ENOMEM; in zorro_esp_probe()
810 /* initialize DMA control shadow register */ in zorro_esp_probe()
811 zep->ctrl_data = (FASTLANE_DMA_FCODE | in zorro_esp_probe()
815 esp->ops = zdd->esp_ops; in zorro_esp_probe()
818 esp->regs = ioremap(ioaddr, 0x20); in zorro_esp_probe()
821 esp->regs = ZTWO_VADDR(ioaddr); in zorro_esp_probe()
823 if (!esp->regs) { in zorro_esp_probe()
824 err = -ENOMEM; in zorro_esp_probe()
828 esp->fifo_reg = esp->regs + ESP_FDATA * 4; in zorro_esp_probe()
831 if (zdd->scsi_option) { in zorro_esp_probe()
834 err = -ENODEV; in zorro_esp_probe()
839 if (zep->zorro3) { in zorro_esp_probe()
841 * Only Fastlane Z3 for now - add switch for correct struct in zorro_esp_probe()
844 esp->dma_regs = ioremap(dmaaddr, in zorro_esp_probe()
848 esp->dma_regs = ZTWO_VADDR(dmaaddr); in zorro_esp_probe()
850 if (!esp->dma_regs) { in zorro_esp_probe()
851 err = -ENOMEM; in zorro_esp_probe()
855 esp->command_block = dma_alloc_coherent(esp->dev, 16, in zorro_esp_probe()
856 &esp->command_block_dma, in zorro_esp_probe()
859 if (!esp->command_block) { in zorro_esp_probe()
860 err = -ENOMEM; in zorro_esp_probe()
864 host->irq = IRQ_AMIGA_PORTS; in zorro_esp_probe()
865 err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, in zorro_esp_probe()
868 err = -ENODEV; in zorro_esp_probe()
876 err = -ENOMEM; in zorro_esp_probe()
883 free_irq(host->irq, esp); in zorro_esp_probe()
886 dma_free_coherent(esp->dev, 16, in zorro_esp_probe()
887 esp->command_block, in zorro_esp_probe()
888 esp->command_block_dma); in zorro_esp_probe()
891 if (zep->zorro3) in zorro_esp_probe()
892 iounmap(esp->dma_regs); in zorro_esp_probe()
896 iounmap(esp->regs); in zorro_esp_probe()
899 if (zep->zorro3) in zorro_esp_probe()
900 iounmap(zep->board_base); in zorro_esp_probe()
916 struct zorro_esp_priv *zep = dev_get_drvdata(&z->dev); in zorro_esp_remove()
917 struct esp *esp = zep->esp; in zorro_esp_remove()
918 struct Scsi_Host *host = esp->host; in zorro_esp_remove()
922 free_irq(host->irq, esp); in zorro_esp_remove()
923 dma_free_coherent(esp->dev, 16, in zorro_esp_remove()
924 esp->command_block, in zorro_esp_remove()
925 esp->command_block_dma); in zorro_esp_remove()
927 if (zep->zorro3) { in zorro_esp_remove()
928 iounmap(zep->board_base); in zorro_esp_remove()
929 iounmap(esp->dma_regs); in zorro_esp_remove()
932 if (host->base > 0xffffff) in zorro_esp_remove()
933 iounmap(esp->regs); in zorro_esp_remove()