Lines Matching +full:0 +full:x3500
11 #define QLA83XX_FLASH_SPI_STATUS 0x2808E010
12 #define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
13 #define QLA83XX_FLASH_STATUS 0x42100004
14 #define QLA83XX_FLASH_CONTROL 0x42110004
15 #define QLA83XX_FLASH_ADDR 0x42110008
16 #define QLA83XX_FLASH_WRDATA 0x4211000C
17 #define QLA83XX_FLASH_RDDATA 0x42110018
18 #define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
19 #define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
24 #define QLA83XX_FLASH_LOCK 0x3850
25 #define QLA83XX_FLASH_UNLOCK 0x3854
26 #define QLA83XX_FLASH_LOCK_ID 0x3500
29 #define QLA83XX_DRV_LOCK 0x3868
30 #define QLA83XX_DRV_UNLOCK 0x386C
31 #define QLA83XX_DRV_LOCK_ID 0x3504
32 #define QLA83XX_DRV_LOCKRECOVERY 0x379C
35 #define QLA83XX_IDC_VER_MAJ_VALUE 0x1
36 #define QLA83XX_IDC_VER_MIN_VALUE 0x0
39 #define QLA83XX_CRB_IDC_VER_MAJOR 0x3780
40 #define QLA83XX_CRB_IDC_VER_MINOR 0x3798
41 #define QLA83XX_IDC_DRV_CTRL 0x3790
42 #define QLA83XX_IDC_DRV_AUDIT 0x3794
43 #define QLA83XX_SRE_SHIM_CONTROL 0x0D200284
44 #define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4
45 #define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4
46 #define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388
47 #define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388
48 #define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C
49 #define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C
50 #define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704
51 #define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704
54 #define QLA83XX_SET_PAUSE_VAL 0x0
55 #define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF
57 #define QLA83XX_RESET_CONTROL 0x28084E50
58 #define QLA83XX_RESET_REG 0x28084E60
59 #define QLA83XX_RESET_PORT0 0x28084E70
60 #define QLA83XX_RESET_PORT1 0x28084E80
61 #define QLA83XX_RESET_PORT2 0x28084E90
62 #define QLA83XX_RESET_PORT3 0x28084EA0
63 #define QLA83XX_RESET_SRE_SHIM 0x28084EB0
64 #define QLA83XX_RESET_EPG_SHIM 0x28084EC0
65 #define QLA83XX_RESET_ETHER_PCS 0x28084ED0
68 #define QLA83XX_PEG_HALT_STATUS1 0x34A8
69 #define QLA83XX_PEG_HALT_STATUS2 0x34AC
70 #define QLA83XX_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
71 #define QLA83XX_FW_CAPABILITIES 0x3528
72 #define QLA83XX_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
73 #define QLA83XX_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
74 #define QLA83XX_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
75 #define QLA83XX_CRB_DRV_SCRATCH 0x3548
76 #define QLA83XX_CRB_DEV_PART_INFO1 0x37E0
77 #define QLA83XX_CRB_DEV_PART_INFO2 0x37E4
79 #define QLA83XX_FW_VER_MAJOR 0x3550
80 #define QLA83XX_FW_VER_MINOR 0x3554
81 #define QLA83XX_FW_VER_SUB 0x3558
82 #define QLA83XX_NPAR_STATE 0x359C
83 #define QLA83XX_FW_IMAGE_VALID 0x35FC
84 #define QLA83XX_CMDPEG_STATE 0x3650
85 #define QLA83XX_ASIC_TEMP 0x37B4
86 #define QLA83XX_FW_API 0x356C
87 #define QLA83XX_DRV_OP_MODE 0x3570
89 #define QLA83XX_CRB_WIN_BASE 0x3800
91 #define QLA83XX_SEM_LOCK_BASE 0x3840
92 #define QLA83XX_SEM_UNLOCK_BASE 0x3844
95 #define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
96 #define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
97 #define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
105 #define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
106 #define QLA83XX_FLASH_WRITE_CMD 0xdacdacda
107 #define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca
109 #define QLA83XX_FLASH_STATUS_READY 0x6
117 #define QLA83XX_GLOBAL_RESET 0x38CC
118 #define QLA83XX_WILDCARD 0x38F0
119 #define QLA83XX_INFORMANT 0x38FC
120 #define QLA83XX_HOST_MBX_CTRL 0x3038
121 #define QLA83XX_FW_MBX_CTRL 0x303C
122 #define QLA83XX_BOOTLOADER_ADDR 0x355C
123 #define QLA83XX_BOOTLOADER_SIZE 0x3560
124 #define QLA83XX_FW_IMAGE_ADDR 0x3564
125 #define QLA83XX_MBX_INTR_ENABLE 0x1000
126 #define QLA83XX_MBX_INTR_MASK 0x1200
129 #define DONTRESET_BIT0 0x1
130 #define GRACEFUL_RESET_BIT1 0x2
132 #define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29)
133 #define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29)
134 #define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
137 #define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000
138 #define QLA83XX_BOOT_FROM_FLASH 0
140 #define QLA83XX_IDC_PARAM_ADDR 0x3e8020
143 #define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000
144 #define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000
145 #define QLA83XX_RESET_SEQ_VERSION 0x0101
148 #define OPCODE_NOP 0x0000
149 #define OPCODE_WRITE_LIST 0x0001
150 #define OPCODE_READ_WRITE_LIST 0x0002
151 #define OPCODE_POLL_LIST 0x0004
152 #define OPCODE_POLL_WRITE_LIST 0x0008
153 #define OPCODE_READ_MODIFY_WRITE 0x0010
154 #define OPCODE_SEQ_PAUSE 0x0020
155 #define OPCODE_SEQ_END 0x0040
156 #define OPCODE_TMPL_END 0x0080
157 #define OPCODE_POLL_READ_LIST 0x0100
160 #define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
320 #define QLA83XX_PEX_DMA_BASE_ADDRESS 0x77320000
321 #define QLA83XX_PEX_DMA_NUM_OFFSET 0x10000
322 #define QLA83XX_PEX_DMA_CMD_ADDR_LOW 0x0
323 #define QLA83XX_PEX_DMA_CMD_ADDR_HIGH 0x04
324 #define QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL 0x08
343 uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
348 uint64_t dma_bus_addr; /* 0-3: desc-cmd, 4-7: pci-func,