Lines Matching +full:memcpy +full:- +full:burst +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2003-2014 QLogic Corporation
18 * qla2x00_lock_nvram_access() -
25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_lock_nvram_access()
28 data = rd_reg_word(®->nvram); in qla2x00_lock_nvram_access()
31 data = rd_reg_word(®->nvram); in qla2x00_lock_nvram_access()
35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
36 rd_reg_word(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
38 data = rd_reg_word(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); in qla2x00_lock_nvram_access()
43 rd_reg_word(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
45 data = rd_reg_word(®->u.isp2300.host_semaphore); in qla2x00_lock_nvram_access()
51 * qla2x00_unlock_nvram_access() -
57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_unlock_nvram_access()
60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); in qla2x00_unlock_nvram_access()
61 rd_reg_word(®->u.isp2300.host_semaphore); in qla2x00_unlock_nvram_access()
66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_nv_write()
75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); in qla2x00_nv_write()
76 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK | in qla2x00_nv_write()
80 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); in qla2x00_nv_write()
83 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nv_write()
88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
97 * Bit 23-16 = address
98 * Bit 15-0 = write data
106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_nvram_request()
122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK); in qla2x00_nvram_request()
123 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
126 reg_data = rd_reg_word(®->nvram); in qla2x00_nvram_request()
129 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_nvram_request()
130 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
135 wrt_reg_word(®->nvram, NVR_DESELECT); in qla2x00_nvram_request()
136 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nvram_request()
144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
165 * qla2x00_nv_deselect() - Deselect NVRAM operations.
171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_nv_deselect()
173 wrt_reg_word(®->nvram, NVR_DESELECT); in qla2x00_nv_deselect()
174 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_nv_deselect()
179 * qla2x00_write_nvram_word() - Write NVRAM data.
190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_write_nvram_word()
191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla2x00_write_nvram_word()
218 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_write_nvram_word()
219 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_write_nvram_word()
222 if (!--wait_cnt) { in qla2x00_write_nvram_word()
228 word = rd_reg_word(®->nvram); in qla2x00_write_nvram_word()
248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_write_nvram_word_tmo()
277 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_write_nvram_word_tmo()
278 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_write_nvram_word_tmo()
281 word = rd_reg_word(®->nvram); in qla2x00_write_nvram_word_tmo()
282 if (!--tmo) { in qla2x00_write_nvram_word_tmo()
301 * qla2x00_clear_nvram_protection() -
308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_clear_nvram_protection()
311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla2x00_clear_nvram_protection()
316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); in qla2x00_clear_nvram_protection()
317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, in qla2x00_clear_nvram_protection()
319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); in qla2x00_clear_nvram_protection()
349 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_clear_nvram_protection()
350 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_clear_nvram_protection()
353 if (!--wait_cnt) { in qla2x00_clear_nvram_protection()
359 word = rd_reg_word(®->nvram); in qla2x00_clear_nvram_protection()
365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); in qla2x00_clear_nvram_protection()
373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_set_nvram_protection()
375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); in qla2x00_set_nvram_protection()
409 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_set_nvram_protection()
410 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_set_nvram_protection()
413 if (!--wait_cnt) { in qla2x00_set_nvram_protection()
419 word = rd_reg_word(®->nvram); in qla2x00_set_nvram_protection()
431 return ha->flash_conf_off + faddr; in flash_conf_addr()
437 return ha->flash_data_off + faddr; in flash_data_addr()
443 return ha->nvram_conf_off + naddr; in nvram_conf_addr()
449 return ha->nvram_data_off + naddr; in nvram_data_addr()
455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_read_flash_dword()
458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG); in qla24xx_read_flash_dword()
460 while (cnt--) { in qla24xx_read_flash_dword()
461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { in qla24xx_read_flash_dword()
462 *data = rd_reg_dword(®->flash_data); in qla24xx_read_flash_dword()
469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, in qla24xx_read_flash_dword()
481 struct qla_hw_data *ha = vha->hw; in qla24xx_read_flash_data()
498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_write_flash_dword()
501 wrt_reg_dword(®->flash_data, data); in qla24xx_write_flash_dword()
502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG); in qla24xx_write_flash_dword()
504 while (cnt--) { in qla24xx_write_flash_dword()
505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) in qla24xx_write_flash_dword()
511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, in qla24xx_write_flash_dword()
553 struct qla_hw_data *ha = vha->hw; in qla2xxx_find_flt_start()
554 struct req_que *req = ha->req_q_map[0]; in qla2xxx_find_flt_start()
555 struct qla_flt_location *fltl = (void *)req->ring; in qla2xxx_find_flt_start()
556 uint32_t *dcode = (uint32_t *)req->ring; in qla2xxx_find_flt_start()
557 uint8_t *buf = (void *)req->ring, *bcode, last_image; in qla2xxx_find_flt_start()
561 * FLT-location structure resides after the last PCI region. in qla2xxx_find_flt_start()
619 /* Now verify FLT-location structure. */ in qla2xxx_find_flt_start()
626 if (memcmp(fltl->sig, "QFLT", 4)) in qla2xxx_find_flt_start()
629 wptr = (__force __le16 *)req->ring; in qla2xxx_find_flt_start()
631 for (chksum = 0; cnt--; wptr++) in qla2xxx_find_flt_start()
643 *start = (le16_to_cpu(fltl->start_hi) << 16 | in qla2xxx_find_flt_start()
644 le16_to_cpu(fltl->start_lo)) >> 2; in qla2xxx_find_flt_start()
686 struct qla_hw_data *ha = vha->hw; in qla2xxx_get_flt_info()
688 struct qla_flt_header *flt = ha->flt; in qla2xxx_get_flt_info()
689 struct qla_flt_region *region = &flt->region[0]; in qla2xxx_get_flt_info()
697 ha->flt_region_fcp_prio = (ha->port_no == 0) ? in qla2xxx_get_flt_info()
700 ha->flt_region_flt = flt_addr; in qla2xxx_get_flt_info()
701 wptr = (__force __le16 *)ha->flt; in qla2xxx_get_flt_info()
702 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2, in qla2xxx_get_flt_info()
707 if (flt->version != cpu_to_le16(1)) { in qla2xxx_get_flt_info()
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length), in qla2xxx_get_flt_info()
711 le16_to_cpu(flt->checksum)); in qla2xxx_get_flt_info()
715 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); in qla2xxx_get_flt_info()
716 for (chksum = 0; cnt--; wptr++) in qla2xxx_get_flt_info()
721 le16_to_cpu(flt->version), le16_to_cpu(flt->length), in qla2xxx_get_flt_info()
722 le16_to_cpu(flt->checksum)); in qla2xxx_get_flt_info()
726 cnt = le16_to_cpu(flt->length) / sizeof(*region); in qla2xxx_get_flt_info()
727 for ( ; cnt; cnt--, region++) { in qla2xxx_get_flt_info()
729 start = le32_to_cpu(region->start) >> 2; in qla2xxx_get_flt_info()
731 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", in qla2xxx_get_flt_info()
732 le16_to_cpu(region->code), start, in qla2xxx_get_flt_info()
733 le32_to_cpu(region->end) >> 2, in qla2xxx_get_flt_info()
734 le32_to_cpu(region->size) >> 2); in qla2xxx_get_flt_info()
735 if (region->attribute) in qla2xxx_get_flt_info()
737 "Region %x is secure\n", region->code); in qla2xxx_get_flt_info()
739 switch (le16_to_cpu(region->code)) { in qla2xxx_get_flt_info()
743 ha->flt_region_fw = start; in qla2xxx_get_flt_info()
748 ha->flt_region_fw = start; in qla2xxx_get_flt_info()
751 ha->flt_region_boot = start; in qla2xxx_get_flt_info()
756 ha->flt_region_vpd_nvram = start; in qla2xxx_get_flt_info()
759 if (ha->port_no == 0) in qla2xxx_get_flt_info()
760 ha->flt_region_vpd = start; in qla2xxx_get_flt_info()
765 if (ha->port_no == 1) in qla2xxx_get_flt_info()
766 ha->flt_region_vpd = start; in qla2xxx_get_flt_info()
771 if (ha->port_no == 2) in qla2xxx_get_flt_info()
772 ha->flt_region_vpd = start; in qla2xxx_get_flt_info()
777 if (ha->port_no == 3) in qla2xxx_get_flt_info()
778 ha->flt_region_vpd = start; in qla2xxx_get_flt_info()
783 if (ha->port_no == 0) in qla2xxx_get_flt_info()
784 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
789 if (ha->port_no == 1) in qla2xxx_get_flt_info()
790 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
795 if (ha->port_no == 2) in qla2xxx_get_flt_info()
796 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
801 if (ha->port_no == 3) in qla2xxx_get_flt_info()
802 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
805 ha->flt_region_fdt = start; in qla2xxx_get_flt_info()
808 if (ha->port_no == 0) in qla2xxx_get_flt_info()
809 ha->flt_region_npiv_conf = start; in qla2xxx_get_flt_info()
812 if (ha->port_no == 1) in qla2xxx_get_flt_info()
813 ha->flt_region_npiv_conf = start; in qla2xxx_get_flt_info()
816 ha->flt_region_gold_fw = start; in qla2xxx_get_flt_info()
819 if (ha->port_no == 0) in qla2xxx_get_flt_info()
820 ha->flt_region_fcp_prio = start; in qla2xxx_get_flt_info()
823 if (ha->port_no == 1) in qla2xxx_get_flt_info()
824 ha->flt_region_fcp_prio = start; in qla2xxx_get_flt_info()
827 ha->flt_region_boot = start; in qla2xxx_get_flt_info()
831 ha->flt_region_boot = start; in qla2xxx_get_flt_info()
834 ha->flt_region_fw = start; in qla2xxx_get_flt_info()
838 ha->flt_region_fw = start; in qla2xxx_get_flt_info()
841 ha->flt_region_gold_fw = start; in qla2xxx_get_flt_info()
844 ha->flt_region_bootload = start; in qla2xxx_get_flt_info()
848 ha->flt_region_vpd = start; in qla2xxx_get_flt_info()
853 if (ha->port_no == 0) in qla2xxx_get_flt_info()
854 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
859 if (ha->port_no == 1) in qla2xxx_get_flt_info()
860 ha->flt_region_nvram = start; in qla2xxx_get_flt_info()
864 ha->flt_region_img_status_pri = start; in qla2xxx_get_flt_info()
868 ha->flt_region_img_status_sec = start; in qla2xxx_get_flt_info()
872 ha->flt_region_fw_sec = start; in qla2xxx_get_flt_info()
876 ha->flt_region_boot_sec = start; in qla2xxx_get_flt_info()
880 ha->flt_region_aux_img_status_pri = start; in qla2xxx_get_flt_info()
884 ha->flt_region_aux_img_status_sec = start; in qla2xxx_get_flt_info()
888 if (ha->port_no == 0) in qla2xxx_get_flt_info()
889 ha->flt_region_nvram_sec = start; in qla2xxx_get_flt_info()
893 if (ha->port_no == 1) in qla2xxx_get_flt_info()
894 ha->flt_region_nvram_sec = start; in qla2xxx_get_flt_info()
898 if (ha->port_no == 2) in qla2xxx_get_flt_info()
899 ha->flt_region_nvram_sec = start; in qla2xxx_get_flt_info()
903 if (ha->port_no == 3) in qla2xxx_get_flt_info()
904 ha->flt_region_nvram_sec = start; in qla2xxx_get_flt_info()
909 ha->flt_region_vpd_nvram_sec = start; in qla2xxx_get_flt_info()
910 if (ha->port_no == 0) in qla2xxx_get_flt_info()
911 ha->flt_region_vpd_sec = start; in qla2xxx_get_flt_info()
917 if (ha->port_no == 1) in qla2xxx_get_flt_info()
918 ha->flt_region_vpd_sec = start; in qla2xxx_get_flt_info()
923 if (ha->port_no == 2) in qla2xxx_get_flt_info()
924 ha->flt_region_vpd_sec = start; in qla2xxx_get_flt_info()
929 if (ha->port_no == 3) in qla2xxx_get_flt_info()
930 ha->flt_region_vpd_sec = start; in qla2xxx_get_flt_info()
939 ha->flt_region_fw = def_fw[def]; in qla2xxx_get_flt_info()
940 ha->flt_region_boot = def_boot[def]; in qla2xxx_get_flt_info()
941 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; in qla2xxx_get_flt_info()
942 ha->flt_region_vpd = (ha->port_no == 0) ? in qla2xxx_get_flt_info()
944 ha->flt_region_nvram = (ha->port_no == 0) ? in qla2xxx_get_flt_info()
946 ha->flt_region_fdt = def_fdt[def]; in qla2xxx_get_flt_info()
947 ha->flt_region_npiv_conf = (ha->port_no == 0) ? in qla2xxx_get_flt_info()
953 loc, ha->flt_region_boot, ha->flt_region_fw, in qla2xxx_get_flt_info()
954 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, in qla2xxx_get_flt_info()
955 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, in qla2xxx_get_flt_info()
956 ha->flt_region_fcp_prio); in qla2xxx_get_flt_info()
966 struct qla_hw_data *ha = vha->hw; in qla2xxx_get_fdt_info()
967 struct req_que *req = ha->req_q_map[0]; in qla2xxx_get_fdt_info()
969 __le16 *wptr = (__force __le16 *)req->ring; in qla2xxx_get_fdt_info()
970 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; in qla2xxx_get_fdt_info()
974 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, in qla2xxx_get_fdt_info()
978 if (memcmp(fdt->sig, "QLID", 4)) in qla2xxx_get_fdt_info()
987 fdt->sig[0], le16_to_cpu(fdt->version)); in qla2xxx_get_fdt_info()
994 mid = le16_to_cpu(fdt->man_id); in qla2xxx_get_fdt_info()
995 fid = le16_to_cpu(fdt->id); in qla2xxx_get_fdt_info()
996 ha->fdt_wrt_disable = fdt->wrt_disable_bits; in qla2xxx_get_fdt_info()
997 ha->fdt_wrt_enable = fdt->wrt_enable_bits; in qla2xxx_get_fdt_info()
998 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; in qla2xxx_get_fdt_info()
1000 ha->fdt_erase_cmd = fdt->erase_cmd; in qla2xxx_get_fdt_info()
1002 ha->fdt_erase_cmd = in qla2xxx_get_fdt_info()
1003 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); in qla2xxx_get_fdt_info()
1004 ha->fdt_block_size = le32_to_cpu(fdt->block_size); in qla2xxx_get_fdt_info()
1005 if (fdt->unprotect_sec_cmd) { in qla2xxx_get_fdt_info()
1006 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | in qla2xxx_get_fdt_info()
1007 fdt->unprotect_sec_cmd); in qla2xxx_get_fdt_info()
1008 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? in qla2xxx_get_fdt_info()
1009 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : in qla2xxx_get_fdt_info()
1016 ha->fdt_block_size = FLASH_BLK_SIZE_64K; in qla2xxx_get_fdt_info()
1022 ha->fdt_wrt_disable = 0x9c; in qla2xxx_get_fdt_info()
1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); in qla2xxx_get_fdt_info()
1027 ha->fdt_block_size = FLASH_BLK_SIZE_64K; in qla2xxx_get_fdt_info()
1029 ha->fdt_block_size = FLASH_BLK_SIZE_32K; in qla2xxx_get_fdt_info()
1032 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); in qla2xxx_get_fdt_info()
1035 ha->fdt_block_size = FLASH_BLK_SIZE_64K; in qla2xxx_get_fdt_info()
1038 ha->fdt_block_size = FLASH_BLK_SIZE_4K; in qla2xxx_get_fdt_info()
1039 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); in qla2xxx_get_fdt_info()
1040 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); in qla2xxx_get_fdt_info()
1041 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); in qla2xxx_get_fdt_info()
1044 /* Default to 64 kb sector size. */ in qla2xxx_get_fdt_info()
1045 ha->fdt_block_size = FLASH_BLK_SIZE_64K; in qla2xxx_get_fdt_info()
1053 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, in qla2xxx_get_fdt_info()
1054 ha->fdt_wrt_disable, ha->fdt_block_size); in qla2xxx_get_fdt_info()
1063 struct qla_hw_data *ha = vha->hw; in qla2xxx_get_idc_param()
1064 struct req_que *req = ha->req_q_map[0]; in qla2xxx_get_idc_param()
1069 wptr = (__force __le32 *)req->ring; in qla2xxx_get_idc_param()
1070 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); in qla2xxx_get_idc_param()
1073 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; in qla2xxx_get_idc_param()
1074 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; in qla2xxx_get_idc_param()
1076 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); in qla2xxx_get_idc_param()
1078 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); in qla2xxx_get_idc_param()
1082 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, in qla2xxx_get_idc_param()
1083 ha->fcoe_reset_timeout); in qla2xxx_get_idc_param()
1092 struct qla_hw_data *ha = vha->hw; in qla2xxx_get_flash_info()
1120 struct qla_hw_data *ha = vha->hw; in qla2xxx_flash_npiv_conf()
1126 if (ha->flags.nic_core_reset_hdlr_active) in qla2xxx_flash_npiv_conf()
1132 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, in qla2xxx_flash_npiv_conf()
1138 "Unsupported NPIV-Config " in qla2xxx_flash_npiv_conf()
1152 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, in qla2xxx_flash_npiv_conf()
1156 for (wptr = data, chksum = 0; cnt--; wptr++) in qla2xxx_flash_npiv_conf()
1160 "Inconsistent NPIV-Config " in qla2xxx_flash_npiv_conf()
1169 for (i = 0; cnt; cnt--, entry++, i++) { in qla2xxx_flash_npiv_conf()
1174 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); in qla2xxx_flash_npiv_conf()
1176 flags = le16_to_cpu(entry->flags); in qla2xxx_flash_npiv_conf()
1186 vid.port_name = wwn_to_u64(entry->port_name); in qla2xxx_flash_npiv_conf()
1187 vid.node_name = wwn_to_u64(entry->node_name); in qla2xxx_flash_npiv_conf()
1192 le16_to_cpu(entry->vf_id), in qla2xxx_flash_npiv_conf()
1193 entry->q_qos, entry->f_qos); in qla2xxx_flash_npiv_conf()
1196 vport = fc_vport_create(vha->host, 0, &vid); in qla2xxx_flash_npiv_conf()
1199 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", in qla2xxx_flash_npiv_conf()
1210 struct qla_hw_data *ha = vha->hw; in qla24xx_unprotect_flash()
1211 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_unprotect_flash()
1213 if (ha->flags.fac_supported) in qla24xx_unprotect_flash()
1217 wrt_reg_dword(®->ctrl_status, in qla24xx_unprotect_flash()
1218 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_unprotect_flash()
1219 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_unprotect_flash()
1221 if (!ha->fdt_wrt_disable) in qla24xx_unprotect_flash()
1224 /* Disable flash write-protection, first clear SR protection bit */ in qla24xx_unprotect_flash()
1235 struct qla_hw_data *ha = vha->hw; in qla24xx_protect_flash()
1236 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_protect_flash()
1240 if (ha->flags.fac_supported) in qla24xx_protect_flash()
1243 if (!ha->fdt_wrt_disable) in qla24xx_protect_flash()
1246 /* Enable flash write-protection and wait for completion. */ in qla24xx_protect_flash()
1248 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); in qla24xx_protect_flash()
1250 while (cnt--) { in qla24xx_protect_flash()
1260 wrt_reg_dword(®->ctrl_status, in qla24xx_protect_flash()
1261 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_protect_flash()
1269 struct qla_hw_data *ha = vha->hw; in qla24xx_erase_sector()
1272 if (ha->flags.fac_supported) { in qla24xx_erase_sector()
1274 finish = start + (ha->fdt_block_size >> 2) - 1; in qla24xx_erase_sector()
1279 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, in qla24xx_erase_sector()
1290 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ in qla24xx_write_flash_data()
1294 struct qla_hw_data *ha = vha->hw; in qla24xx_write_flash_data()
1300 /* Allocate dma buffer for burst write */ in qla24xx_write_flash_data()
1301 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, in qla24xx_write_flash_data()
1305 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); in qla24xx_write_flash_data()
1318 rest_addr = (ha->fdt_block_size >> 2) - 1; in qla24xx_write_flash_data()
1337 /* If smaller than a burst remaining */ in qla24xx_write_flash_data()
1338 if (dwords - liter < dburst) in qla24xx_write_flash_data()
1339 dburst = dwords - liter; in qla24xx_write_flash_data()
1342 memcpy(optrom, dwptr, dburst << 2); in qla24xx_write_flash_data()
1344 /* Burst write */ in qla24xx_write_flash_data()
1346 "Write burst (%#lx dwords)...\n", dburst); in qla24xx_write_flash_data()
1350 liter += dburst - 1; in qla24xx_write_flash_data()
1351 faddr += dburst - 1; in qla24xx_write_flash_data()
1352 dwptr += dburst - 1; in qla24xx_write_flash_data()
1357 "Failed burst-write at %x (%p/%#llx)....\n", in qla24xx_write_flash_data()
1361 dma_free_coherent(&ha->pdev->dev, in qla24xx_write_flash_data()
1388 dma_free_coherent(&ha->pdev->dev, in qla24xx_write_flash_data()
1400 struct qla_hw_data *ha = vha->hw; in qla2x00_read_nvram_data()
1417 struct qla_hw_data *ha = vha->hw; in qla24xx_read_nvram_data()
1444 struct qla_hw_data *ha = vha->hw; in qla2x00_write_nvram_data()
1448 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2x00_write_nvram_data()
1451 /* Disable NVRAM write-protection. */ in qla2x00_write_nvram_data()
1461 /* Enable NVRAM write-protection. */ in qla2x00_write_nvram_data()
1465 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2x00_write_nvram_data()
1474 struct qla_hw_data *ha = vha->hw; in qla24xx_write_nvram_data()
1475 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_write_nvram_data()
1486 wrt_reg_dword(®->ctrl_status, in qla24xx_write_nvram_data()
1487 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()
1488 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()
1490 /* Disable NVRAM write-protection. */ in qla24xx_write_nvram_data()
1506 /* Enable NVRAM write-protection. */ in qla24xx_write_nvram_data()
1510 wrt_reg_dword(®->ctrl_status, in qla24xx_write_nvram_data()
1511 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); in qla24xx_write_nvram_data()
1512 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ in qla24xx_write_nvram_data()
1521 struct qla_hw_data *ha = vha->hw; in qla25xx_read_nvram_data()
1526 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); in qla25xx_read_nvram_data()
1543 struct qla_hw_data *ha = vha->hw; in qla25xx_write_nvram_data()
1548 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, in qla25xx_write_nvram_data()
1550 memcpy(dbuf + (naddr << 2), buf, bytes); in qla25xx_write_nvram_data()
1551 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, in qla25xx_write_nvram_data()
1563 if (ha->beacon_color_state == QLA_LED_ALL_ON) { in qla2x00_flip_colors()
1565 ha->beacon_color_state = 0; in qla2x00_flip_colors()
1569 ha->beacon_color_state = QLA_LED_ALL_ON; in qla2x00_flip_colors()
1574 if (ha->beacon_color_state == QLA_LED_GRN_ON) { in qla2x00_flip_colors()
1576 ha->beacon_color_state = 0; in qla2x00_flip_colors()
1580 ha->beacon_color_state = QLA_LED_GRN_ON; in qla2x00_flip_colors()
1586 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1595 struct qla_hw_data *ha = vha->hw; in qla2x00_beacon_blink()
1596 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_beacon_blink()
1601 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2x00_beacon_blink()
1604 if (ha->pio_address) { in qla2x00_beacon_blink()
1608 gpio_enable = rd_reg_word(®->gpioe); in qla2x00_beacon_blink()
1609 gpio_data = rd_reg_word(®->gpiod); in qla2x00_beacon_blink()
1615 if (ha->pio_address) { in qla2x00_beacon_blink()
1618 wrt_reg_word(®->gpioe, gpio_enable); in qla2x00_beacon_blink()
1619 rd_reg_word(®->gpioe); in qla2x00_beacon_blink()
1631 if (ha->pio_address) { in qla2x00_beacon_blink()
1634 wrt_reg_word(®->gpiod, gpio_data); in qla2x00_beacon_blink()
1635 rd_reg_word(®->gpiod); in qla2x00_beacon_blink()
1638 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2x00_beacon_blink()
1647 struct qla_hw_data *ha = vha->hw; in qla2x00_beacon_on()
1648 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_beacon_on()
1650 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; in qla2x00_beacon_on()
1651 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; in qla2x00_beacon_on()
1653 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { in qla2x00_beacon_on()
1660 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2x00_beacon_on()
1661 if (ha->pio_address) { in qla2x00_beacon_on()
1665 gpio_enable = rd_reg_word(®->gpioe); in qla2x00_beacon_on()
1666 gpio_data = rd_reg_word(®->gpiod); in qla2x00_beacon_on()
1671 if (ha->pio_address) { in qla2x00_beacon_on()
1674 wrt_reg_word(®->gpioe, gpio_enable); in qla2x00_beacon_on()
1675 rd_reg_word(®->gpioe); in qla2x00_beacon_on()
1680 if (ha->pio_address) { in qla2x00_beacon_on()
1683 wrt_reg_word(®->gpiod, gpio_data); in qla2x00_beacon_on()
1684 rd_reg_word(®->gpiod); in qla2x00_beacon_on()
1686 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2x00_beacon_on()
1692 ha->beacon_blink_led = 1; in qla2x00_beacon_on()
1693 ha->beacon_color_state = 0; in qla2x00_beacon_on()
1702 struct qla_hw_data *ha = vha->hw; in qla2x00_beacon_off()
1704 ha->beacon_blink_led = 0; in qla2x00_beacon_off()
1708 ha->beacon_color_state = QLA_LED_ALL_ON; in qla2x00_beacon_off()
1710 ha->beacon_color_state = QLA_LED_GRN_ON; in qla2x00_beacon_off()
1712 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ in qla2x00_beacon_off()
1714 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; in qla2x00_beacon_off()
1715 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; in qla2x00_beacon_off()
1717 rval = qla2x00_set_fw_options(vha, ha->fw_options); in qla2x00_beacon_off()
1729 if (ha->beacon_color_state == QLA_LED_ALL_ON) { in qla24xx_flip_colors()
1731 ha->beacon_color_state = 0; in qla24xx_flip_colors()
1735 ha->beacon_color_state = QLA_LED_ALL_ON; in qla24xx_flip_colors()
1746 struct qla_hw_data *ha = vha->hw; in qla24xx_beacon_blink()
1747 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_beacon_blink()
1750 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_beacon_blink()
1751 gpio_data = rd_reg_dword(®->gpiod); in qla24xx_beacon_blink()
1756 wrt_reg_dword(®->gpiod, gpio_data); in qla24xx_beacon_blink()
1757 gpio_data = rd_reg_dword(®->gpiod); in qla24xx_beacon_blink()
1769 wrt_reg_dword(®->gpiod, gpio_data); in qla24xx_beacon_blink()
1770 gpio_data = rd_reg_dword(®->gpiod); in qla24xx_beacon_blink()
1771 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_beacon_blink()
1782 if (ha->port_no == 0) in qla83xx_select_led_port()
1795 struct qla_hw_data *ha = vha->hw; in qla83xx_beacon_blink()
1804 if (!ha->beacon_blink_led) in qla83xx_beacon_blink()
1874 struct qla_hw_data *ha = vha->hw; in qla24xx_beacon_on()
1875 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_beacon_on()
1883 if (ha->beacon_blink_led == 0) { in qla24xx_beacon_on()
1885 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; in qla24xx_beacon_on()
1887 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) in qla24xx_beacon_on()
1890 if (qla2x00_get_fw_options(vha, ha->fw_options) != in qla24xx_beacon_on()
1900 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_beacon_on()
1901 gpio_data = rd_reg_dword(®->gpiod); in qla24xx_beacon_on()
1905 wrt_reg_dword(®->gpiod, gpio_data); in qla24xx_beacon_on()
1906 rd_reg_dword(®->gpiod); in qla24xx_beacon_on()
1908 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_beacon_on()
1912 ha->beacon_color_state = 0; in qla24xx_beacon_on()
1916 ha->beacon_blink_led = 1; in qla24xx_beacon_on()
1926 struct qla_hw_data *ha = vha->hw; in qla24xx_beacon_off()
1927 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla24xx_beacon_off()
1932 if (!ha->flags.fw_started) in qla24xx_beacon_off()
1935 ha->beacon_blink_led = 0; in qla24xx_beacon_off()
1943 ha->beacon_color_state = QLA_LED_ALL_ON; in qla24xx_beacon_off()
1945 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ in qla24xx_beacon_off()
1948 spin_lock_irqsave(&ha->hardware_lock, flags); in qla24xx_beacon_off()
1949 gpio_data = rd_reg_dword(®->gpiod); in qla24xx_beacon_off()
1953 wrt_reg_dword(®->gpiod, gpio_data); in qla24xx_beacon_off()
1954 rd_reg_dword(®->gpiod); in qla24xx_beacon_off()
1955 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla24xx_beacon_off()
1958 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; in qla24xx_beacon_off()
1960 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { in qla24xx_beacon_off()
1966 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { in qla24xx_beacon_off()
1981 * qla2x00_flash_enable() - Setup flash for reading and writing.
1988 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_flash_enable()
1990 data = rd_reg_word(®->ctrl_status); in qla2x00_flash_enable()
1992 wrt_reg_word(®->ctrl_status, data); in qla2x00_flash_enable()
1993 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_flash_enable()
1997 * qla2x00_flash_disable() - Disable flash and allow RISC to run.
2004 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_flash_disable()
2006 data = rd_reg_word(®->ctrl_status); in qla2x00_flash_disable()
2008 wrt_reg_word(®->ctrl_status, data); in qla2x00_flash_disable()
2009 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_flash_disable()
2013 * qla2x00_read_flash_byte() - Reads a byte from flash
2026 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_read_flash_byte()
2028 bank_select = rd_reg_word(®->ctrl_status); in qla2x00_read_flash_byte()
2036 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_read_flash_byte()
2037 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
2039 wrt_reg_word(®->flash_address, (uint16_t)addr); in qla2x00_read_flash_byte()
2040 data = rd_reg_word(®->flash_data); in qla2x00_read_flash_byte()
2048 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_read_flash_byte()
2049 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
2053 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_read_flash_byte()
2054 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_read_flash_byte()
2058 if (ha->pio_address) { in qla2x00_read_flash_byte()
2069 wrt_reg_word(®->flash_address, (uint16_t)addr); in qla2x00_read_flash_byte()
2070 data = qla2x00_debounce_register(®->flash_data); in qla2x00_read_flash_byte()
2077 * qla2x00_write_flash_byte() - Write a byte to flash
2086 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_write_flash_byte()
2088 bank_select = rd_reg_word(®->ctrl_status); in qla2x00_write_flash_byte()
2095 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_write_flash_byte()
2096 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2098 wrt_reg_word(®->flash_address, (uint16_t)addr); in qla2x00_write_flash_byte()
2099 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2100 wrt_reg_word(®->flash_data, (uint16_t)data); in qla2x00_write_flash_byte()
2101 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2109 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_write_flash_byte()
2110 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2114 wrt_reg_word(®->ctrl_status, bank_select); in qla2x00_write_flash_byte()
2115 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2119 if (ha->pio_address) { in qla2x00_write_flash_byte()
2123 wrt_reg_word(®->flash_address, (uint16_t)addr); in qla2x00_write_flash_byte()
2124 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2125 wrt_reg_word(®->flash_data, (uint16_t)data); in qla2x00_write_flash_byte()
2126 rd_reg_word(®->ctrl_status); /* PCI Posting. */ in qla2x00_write_flash_byte()
2131 * qla2x00_poll_flash() - Polls flash for completion.
2143 * Returns 0 on success, else non-zero.
2157 for (cnt = 3000000; cnt; cnt--) { in qla2x00_poll_flash()
2176 * qla2x00_program_flash_address() - Programs a flash address
2183 * Returns 0 on success, else non-zero.
2215 * qla2x00_erase_flash() - Erase the flash.
2220 * Returns 0 on success, else non-zero.
2249 * qla2x00_erase_flash_sector() - Erase a flash sector.
2256 * Returns 0 on success, else non-zero.
2280 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
2303 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_read_flash_data()
2309 wrt_reg_word(®->nvram, 0); in qla2x00_read_flash_data()
2310 rd_reg_word(®->nvram); in qla2x00_read_flash_data()
2313 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_read_flash_data()
2314 rd_reg_word(®->nvram); in qla2x00_read_flash_data()
2329 struct qla_hw_data *ha = vha->hw; in qla2x00_suspend_hba()
2330 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_suspend_hba()
2333 scsi_block_requests(vha->host); in qla2x00_suspend_hba()
2334 ha->isp_ops->disable_intrs(ha); in qla2x00_suspend_hba()
2335 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla2x00_suspend_hba()
2338 spin_lock_irqsave(&ha->hardware_lock, flags); in qla2x00_suspend_hba()
2339 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); in qla2x00_suspend_hba()
2340 rd_reg_word(®->hccr); in qla2x00_suspend_hba()
2343 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) in qla2x00_suspend_hba()
2350 spin_unlock_irqrestore(&ha->hardware_lock, flags); in qla2x00_suspend_hba()
2356 struct qla_hw_data *ha = vha->hw; in qla2x00_resume_hba()
2359 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla2x00_resume_hba()
2360 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); in qla2x00_resume_hba()
2363 scsi_unblock_requests(vha->host); in qla2x00_resume_hba()
2372 struct qla_hw_data *ha = vha->hw; in qla2x00_read_optrom_data()
2373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_read_optrom_data()
2379 midpoint = ha->optrom_size / 2; in qla2x00_read_optrom_data()
2382 wrt_reg_word(®->nvram, 0); in qla2x00_read_optrom_data()
2383 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_read_optrom_data()
2386 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_read_optrom_data()
2387 rd_reg_word(®->nvram); /* PCI Posting. */ in qla2x00_read_optrom_data()
2409 struct qla_hw_data *ha = vha->hw; in qla2x00_write_optrom_data()
2410 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; in qla2x00_write_optrom_data()
2419 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); in qla2x00_write_optrom_data()
2420 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); in qla2x00_write_optrom_data()
2438 * ST m29w008at part - 64kb sector size with in qla2x00_write_optrom_data()
2447 * ST m29w010b part - 16kb sector size in qla2x00_write_optrom_data()
2454 /* Mostel v29c51001 part - 512 byte sector size. */ in qla2x00_write_optrom_data()
2459 /* SST39sf10 part - 4kb sector size. */ in qla2x00_write_optrom_data()
2464 /* Winbond W29EE011 part - 256 byte sector size. */ in qla2x00_write_optrom_data()
2469 /* 64k sector size. */ in qla2x00_write_optrom_data()
2478 /* 512k sector size. */ in qla2x00_write_optrom_data()
2489 /* Am29LV081 part - 64kb sector size. */ in qla2x00_write_optrom_data()
2490 /* Am29LV002BT part - 64kb sector size. */ in qla2x00_write_optrom_data()
2496 * Am29LV008b part - 64kb sector size with in qla2x00_write_optrom_data()
2505 * Am29LV010 part or AM29f010 - 16kb sector in qla2x00_write_optrom_data()
2506 * size. in qla2x00_write_optrom_data()
2512 /* Am29LV001 part - 8kb sector size. */ in qla2x00_write_optrom_data()
2519 /* Default to 16 kb sector size. */ in qla2x00_write_optrom_data()
2567 } else if (addr == ha->optrom_size / 2) { in qla2x00_write_optrom_data()
2568 wrt_reg_word(®->nvram, NVR_SELECT); in qla2x00_write_optrom_data()
2569 rd_reg_word(®->nvram); in qla2x00_write_optrom_data()
2594 addr == (rest_addr - 1)) { in qla2x00_write_optrom_data()
2623 struct qla_hw_data *ha = vha->hw; in qla24xx_read_optrom_data()
2627 scsi_block_requests(vha->host); in qla24xx_read_optrom_data()
2628 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla24xx_read_optrom_data()
2638 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla24xx_read_optrom_data()
2639 scsi_unblock_requests(vha->host); in qla24xx_read_optrom_data()
2655 memcpy(sfub_buf, (uint8_t *)p, in qla28xx_extract_sfub_and_verify()
2677 struct qla_hw_data *ha = vha->hw; in qla28xx_get_flash_region()
2678 struct qla_flt_header *flt = ha->flt; in qla28xx_get_flash_region()
2679 struct qla_flt_region *flt_reg = &flt->region[0]; in qla28xx_get_flash_region()
2683 if (!ha->flt) in qla28xx_get_flash_region()
2686 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); in qla28xx_get_flash_region()
2687 for (; cnt; cnt--, flt_reg++) { in qla28xx_get_flash_region()
2688 if (le32_to_cpu(flt_reg->start) == start) { in qla28xx_get_flash_region()
2689 memcpy((uint8_t *)region, flt_reg, in qla28xx_get_flash_region()
2703 struct qla_hw_data *ha = vha->hw; in qla28xx_write_flash_data()
2705 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ in qla28xx_write_flash_data()
2719 /* Retrieve region info - must be a start address passed in */ in qla28xx_write_flash_data()
2724 "Invalid address %x - not a region start address\n", in qla28xx_write_flash_data()
2729 /* Allocate dma buffer for burst write */ in qla28xx_write_flash_data()
2730 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, in qla28xx_write_flash_data()
2734 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); in qla28xx_write_flash_data()
2743 if (ha->flags.secure_adapter && region.attribute) { in qla28xx_write_flash_data()
2805 sfub = dma_alloc_coherent(&ha->pdev->dev, in qla28xx_write_flash_data()
2825 rest_addr = (ha->fdt_block_size >> 2) - 1; in qla28xx_write_flash_data()
2861 if (ha->flags.secure_adapter) { in qla28xx_write_flash_data()
2867 if (!ha->flags.secure_fw) { in qla28xx_write_flash_data()
2881 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); in qla28xx_write_flash_data()
2882 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); in qla28xx_write_flash_data()
2891 ha->flags.fac_supported = 0; in qla28xx_write_flash_data()
2931 /* re-init flash offset */ in qla28xx_write_flash_data()
2937 /* If smaller than a burst remaining */ in qla28xx_write_flash_data()
2938 if (dwords - liter < dburst) in qla28xx_write_flash_data()
2939 dburst = dwords - liter; in qla28xx_write_flash_data()
2942 memcpy(optrom, dwptr, dburst << 2); in qla28xx_write_flash_data()
2944 /* Burst write */ in qla28xx_write_flash_data()
2946 "Write burst (%#lx dwords)...\n", dburst); in qla28xx_write_flash_data()
2951 "Failed burst write at %x (%p/%#llx)...\n", in qla28xx_write_flash_data()
2957 liter += dburst - 1; in qla28xx_write_flash_data()
2958 faddr += dburst - 1; in qla28xx_write_flash_data()
2959 dwptr += dburst - 1; in qla28xx_write_flash_data()
2975 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); in qla28xx_write_flash_data()
2988 dma_free_coherent(&ha->pdev->dev, in qla28xx_write_flash_data()
2999 struct qla_hw_data *ha = vha->hw; in qla24xx_write_optrom_data()
3002 scsi_block_requests(vha->host); in qla24xx_write_optrom_data()
3003 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla24xx_write_optrom_data()
3013 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); in qla24xx_write_optrom_data()
3014 scsi_unblock_requests(vha->host); in qla24xx_write_optrom_data()
3027 uint32_t faddr, left, burst; in qla25xx_read_optrom_data() local
3028 struct qla_hw_data *ha = vha->hw; in qla25xx_read_optrom_data()
3041 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, in qla25xx_read_optrom_data()
3045 "Unable to allocate memory for optrom burst read (%x KB).\n", in qla25xx_read_optrom_data()
3053 burst = OPTROM_BURST_DWORDS; in qla25xx_read_optrom_data()
3055 if (burst > left) in qla25xx_read_optrom_data()
3056 burst = left; in qla25xx_read_optrom_data()
3059 flash_data_addr(ha, faddr), burst); in qla25xx_read_optrom_data()
3062 "Unable to burst-read optrom segment (%x/%x/%llx).\n", in qla25xx_read_optrom_data()
3066 "Reverting to slow-read.\n"); in qla25xx_read_optrom_data()
3068 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, in qla25xx_read_optrom_data()
3073 memcpy(pbuf, optrom, burst * 4); in qla25xx_read_optrom_data()
3075 left -= burst; in qla25xx_read_optrom_data()
3076 faddr += burst; in qla25xx_read_optrom_data()
3077 pbuf += burst * 4; in qla25xx_read_optrom_data()
3080 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, in qla25xx_read_optrom_data()
3090 * qla2x00_get_fcode_version() - Determine an FCODE image's version.
3114 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); in qla2x00_get_fcode_version()
3142 iter--; in qla2x00_get_fcode_version()
3151 * string length (recent FCODE images -- major hack ahead!!!). in qla2x00_get_fcode_version()
3153 vend = iter - 1; in qla2x00_get_fcode_version()
3156 iter--; in qla2x00_get_fcode_version()
3166 if ((vend - iter) && in qla2x00_get_fcode_version()
3167 ((vend - iter) < sizeof(ha->fcode_revision))) { in qla2x00_get_fcode_version()
3168 vbyte = ha->fcode_revision; in qla2x00_get_fcode_version()
3178 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); in qla2x00_get_fcode_version()
3189 struct qla_hw_data *ha = vha->hw; in qla2x00_get_flash_version()
3191 if (!ha->pio_address || !mbuf) in qla2x00_get_flash_version()
3194 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); in qla2x00_get_flash_version()
3195 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); in qla2x00_get_flash_version()
3196 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); in qla2x00_get_flash_version()
3197 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla2x00_get_flash_version()
3236 /* Intel x86, PC-AT compatible. */ in qla2x00_get_flash_version()
3237 ha->bios_revision[0] = in qla2x00_get_flash_version()
3239 ha->bios_revision[1] = in qla2x00_get_flash_version()
3243 ha->bios_revision[1], ha->bios_revision[0]); in qla2x00_get_flash_version()
3252 ha->efi_revision[0] = in qla2x00_get_flash_version()
3254 ha->efi_revision[1] = in qla2x00_get_flash_version()
3258 ha->efi_revision[1], ha->efi_revision[0]); in qla2x00_get_flash_version()
3276 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla2x00_get_flash_version()
3281 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, in qla2x00_get_flash_version()
3295 ha->flt_region_fw * 4); in qla2x00_get_flash_version()
3298 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; in qla2x00_get_flash_version()
3299 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; in qla2x00_get_flash_version()
3300 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; in qla2x00_get_flash_version()
3303 "%d.%d.%d.\n", ha->fw_revision[0], in qla2x00_get_flash_version()
3304 ha->fw_revision[1], ha->fw_revision[2]); in qla2x00_get_flash_version()
3321 struct qla_hw_data *ha = vha->hw; in qla82xx_get_flash_version()
3326 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); in qla82xx_get_flash_version()
3327 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); in qla82xx_get_flash_version()
3328 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); in qla82xx_get_flash_version()
3329 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla82xx_get_flash_version()
3332 pcihdr = ha->flt_region_boot << 2; in qla82xx_get_flash_version()
3336 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); in qla82xx_get_flash_version()
3349 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); in qla82xx_get_flash_version()
3365 /* Intel x86, PC-AT compatible. */ in qla82xx_get_flash_version()
3366 ha->bios_revision[0] = bcode[0x12]; in qla82xx_get_flash_version()
3367 ha->bios_revision[1] = bcode[0x13]; in qla82xx_get_flash_version()
3370 ha->bios_revision[1], ha->bios_revision[0]); in qla82xx_get_flash_version()
3374 ha->fcode_revision[0] = bcode[0x12]; in qla82xx_get_flash_version()
3375 ha->fcode_revision[1] = bcode[0x13]; in qla82xx_get_flash_version()
3378 ha->fcode_revision[1], ha->fcode_revision[0]); in qla82xx_get_flash_version()
3382 ha->efi_revision[0] = bcode[0x12]; in qla82xx_get_flash_version()
3383 ha->efi_revision[1] = bcode[0x13]; in qla82xx_get_flash_version()
3386 ha->efi_revision[1], ha->efi_revision[0]); in qla82xx_get_flash_version()
3402 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla82xx_get_flash_version()
3404 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); in qla82xx_get_flash_version()
3410 ha->fw_revision[0] = bcode[0x4]; in qla82xx_get_flash_version()
3411 ha->fw_revision[1] = bcode[0x5]; in qla82xx_get_flash_version()
3412 ha->fw_revision[2] = bcode[0x6]; in qla82xx_get_flash_version()
3415 ha->fw_revision[0], ha->fw_revision[1], in qla82xx_get_flash_version()
3416 ha->fw_revision[2]); in qla82xx_get_flash_version()
3431 struct qla_hw_data *ha = vha->hw; in qla24xx_get_flash_version()
3441 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); in qla24xx_get_flash_version()
3442 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); in qla24xx_get_flash_version()
3443 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); in qla24xx_get_flash_version()
3444 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla24xx_get_flash_version()
3446 pcihdr = ha->flt_region_boot << 2; in qla24xx_get_flash_version()
3450 pcihdr = ha->flt_region_boot_sec << 2; in qla24xx_get_flash_version()
3496 /* Intel x86, PC-AT compatible. */ in qla24xx_get_flash_version()
3497 ha->bios_revision[0] = bcode[0x12]; in qla24xx_get_flash_version()
3498 ha->bios_revision[1] = bcode[0x13]; in qla24xx_get_flash_version()
3501 ha->bios_revision[1], ha->bios_revision[0]); in qla24xx_get_flash_version()
3505 ha->fcode_revision[0] = bcode[0x12]; in qla24xx_get_flash_version()
3506 ha->fcode_revision[1] = bcode[0x13]; in qla24xx_get_flash_version()
3509 ha->fcode_revision[1], ha->fcode_revision[0]); in qla24xx_get_flash_version()
3513 ha->efi_revision[0] = bcode[0x12]; in qla24xx_get_flash_version()
3514 ha->efi_revision[1] = bcode[0x13]; in qla24xx_get_flash_version()
3517 ha->efi_revision[1], ha->efi_revision[0]); in qla24xx_get_flash_version()
3533 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); in qla24xx_get_flash_version()
3534 faddr = ha->flt_region_fw; in qla24xx_get_flash_version()
3538 faddr = ha->flt_region_fw_sec; in qla24xx_get_flash_version()
3550 ha->flt_region_fw * 4); in qla24xx_get_flash_version()
3554 ha->fw_revision[i] = in qla24xx_get_flash_version()
3558 ha->fw_revision[0], ha->fw_revision[1], in qla24xx_get_flash_version()
3559 ha->fw_revision[2], ha->fw_revision[3]); in qla24xx_get_flash_version()
3569 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); in qla24xx_get_flash_version()
3570 faddr = ha->flt_region_gold_fw; in qla24xx_get_flash_version()
3571 ret = qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8); in qla24xx_get_flash_version()
3585 ha->gold_fw_version[i] = in qla24xx_get_flash_version()
3609 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) in qla2xxx_get_vpd_field() argument
3611 struct qla_hw_data *ha = vha->hw; in qla2xxx_get_vpd_field()
3612 uint8_t *pos = ha->vpd; in qla2xxx_get_vpd_field()
3613 uint8_t *end = pos + ha->vpd_size; in qla2xxx_get_vpd_field()
3631 if (pos < end - len && *pos != 0x78) in qla2xxx_get_vpd_field()
3632 return scnprintf(str, size, "%.*s", len, pos + 3); in qla2xxx_get_vpd_field()
3642 struct qla_hw_data *ha = vha->hw; in qla24xx_read_fcp_prio_cfg()
3644 if (!ha->fcp_prio_cfg) { in qla24xx_read_fcp_prio_cfg()
3645 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); in qla24xx_read_fcp_prio_cfg()
3646 if (!ha->fcp_prio_cfg) { in qla24xx_read_fcp_prio_cfg()
3653 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); in qla24xx_read_fcp_prio_cfg()
3655 fcp_prio_addr = ha->flt_region_fcp_prio; in qla24xx_read_fcp_prio_cfg()
3658 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, in qla24xx_read_fcp_prio_cfg()
3661 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) in qla24xx_read_fcp_prio_cfg()
3666 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry); in qla24xx_read_fcp_prio_cfg()
3667 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; in qla24xx_read_fcp_prio_cfg()
3669 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], in qla24xx_read_fcp_prio_cfg()
3673 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) in qla24xx_read_fcp_prio_cfg()
3676 ha->flags.fcp_prio_enabled = 1; in qla24xx_read_fcp_prio_cfg()
3679 vfree(ha->fcp_prio_cfg); in qla24xx_read_fcp_prio_cfg()
3680 ha->fcp_prio_cfg = NULL; in qla24xx_read_fcp_prio_cfg()