3035 	ha->pci_attr = rd_reg_dword(&reg->ctrl_status);  in qla24xx_pci_config()
3338 		if ((rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)  in qla24xx_reset_risc()
3344 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE))  in qla24xx_reset_risc()
3349 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3350 	    rd_reg_dword(&reg->ctrl_status),  in qla24xx_reset_risc()
3351 	    (rd_reg_dword(&reg->ctrl_status) & CSRX_DMA_ACTIVE));  in qla24xx_reset_risc()
3375 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3379 	rd_reg_dword(&reg->ctrl_status);  in qla24xx_reset_risc()
3382 		if ((rd_reg_dword(&reg->ctrl_status) &  in qla24xx_reset_risc()
3388 	if (!(rd_reg_dword(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))  in qla24xx_reset_risc()
3393 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3394 	    rd_reg_dword(&reg->ctrl_status));  in qla24xx_reset_risc()
3414 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3417 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3421 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3445 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3466 	*data = rd_reg_dword(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFSET);  in qla25xx_read_risc_sema_reg()
7829 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7831 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()