2951 		wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);  in qla2300_pci_config()
2953 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) != 0)  in qla2300_pci_config()
2974 		wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2300_pci_config()
2976 			if ((rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0)  in qla2300_pci_config()
3139 		wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);  in qla2x00_reset_chip()
3142 				if ((rd_reg_word(&reg->hccr) &  in qla2x00_reset_chip()
3148 			rd_reg_word(&reg->hccr);	/* PCI Posting. */  in qla2x00_reset_chip()
3190 		wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_chip()
3191 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3194 		wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_chip()
3195 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3198 	wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);  in qla2x00_reset_chip()
3199 	wrt_reg_word(&reg->hccr, HCCR_CLR_HOST_INT);  in qla2x00_reset_chip()
3222 	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_chip()
3227 	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_chip()
3228 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_chip()
3246 		wrt_reg_word(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);  in qla2x00_reset_chip()
3247 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2x00_reset_chip()
3349 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3375 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3393 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3413 	wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);  in qla24xx_reset_risc()
3414 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3416 	wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);  in qla24xx_reset_risc()
3417 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3419 	wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);  in qla24xx_reset_risc()
3421 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_risc()
3445 	    rd_reg_dword(&reg->hccr),  in qla24xx_reset_risc()
3491 	wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);  in qla25xx_manipulate_risc_semaphore()
3614 	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_chip_diag()
3615 	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_chip_diag()
4294 		wrt_reg_word(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));  in qla2x00_setup_chip()
4295 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4400 			wrt_reg_word(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);  in qla2x00_setup_chip()
4403 			wrt_reg_word(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);  in qla2x00_setup_chip()
4404 		rd_reg_word(&reg->hccr);  in qla2x00_setup_chip()
4749 	rd_reg_word(&ioreg->hccr);  in qla24xx_config_rings()
7805 	wrt_reg_word(&reg->hccr, HCCR_RESET_RISC);  in qla2x00_reset_adapter()
7806 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7807 	wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2x00_reset_adapter()
7808 	rd_reg_word(&reg->hccr);			/* PCI Posting. */  in qla2x00_reset_adapter()
7828 	wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);  in qla24xx_reset_adapter()
7829 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()
7830 	wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);  in qla24xx_reset_adapter()
7831 	rd_reg_dword(&reg->hccr);  in qla24xx_reset_adapter()