Lines Matching refs:BIT_5
112 #define BIT_5 0x20 macro
420 #define SRB_CRC_CTX_DSD_VALID BIT_5 /* DIF: dsd_list valid */
538 #define SRB_LOGIN_FCSP BIT_5
924 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
1243 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
1264 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
1418 #define MBX_5 BIT_5
2012 #define CF_READ BIT_5
2080 #define PO_DISABLE_INCR_REF_TAG BIT_5
2172 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
2417 #define NOTIFY24XX_FLAGS_FCSP BIT_5
2604 #define NVME_PRLI_SP_INITIATOR BIT_5
2768 #define FCF_ASYNC_ACTIVE BIT_5
4274 #define DT_ISP6312 BIT_5
4562 #define FW_ATTR_EXT0_EDIF BIT_5
4996 #define DFLG_DEV_FAILED BIT_5
5382 #define FC_LL_I BIT_5 /* Intermidiate*/
5392 #define FC_TEC_SL BIT_5 /* short wave with OFC */
5400 #define FC_MED_MI BIT_5 /* Min Coax */
5409 #define FC_SP_16 BIT_5