1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * Copyright (c)  2003-2014 QLogic Corporation
15 #include <linux/dma-mapping.h>
158 static inline u8 rd_reg_byte(const volatile u8 __iomem *addr)  in rd_reg_byte()  argument
160 	return readb(addr);  in rd_reg_byte()
163 static inline u16 rd_reg_word(const volatile __le16 __iomem *addr)  in rd_reg_word()  argument
165 	return readw(addr);  in rd_reg_word()
168 static inline u32 rd_reg_dword(const volatile __le32 __iomem *addr)  in rd_reg_dword()  argument
170 	return readl(addr);  in rd_reg_dword()
173 static inline u8 rd_reg_byte_relaxed(const volatile u8 __iomem *addr)  in rd_reg_byte_relaxed()  argument
175 	return readb_relaxed(addr);  in rd_reg_byte_relaxed()
178 static inline u16 rd_reg_word_relaxed(const volatile __le16 __iomem *addr)  in rd_reg_word_relaxed()  argument
180 	return readw_relaxed(addr);  in rd_reg_word_relaxed()
183 static inline u32 rd_reg_dword_relaxed(const volatile __le32 __iomem *addr)  in rd_reg_dword_relaxed()  argument
185 	return readl_relaxed(addr);  in rd_reg_dword_relaxed()
188 static inline void wrt_reg_byte(volatile u8 __iomem *addr, u8 data)  in wrt_reg_byte()  argument
190 	return writeb(data, addr);  in wrt_reg_byte()
193 static inline void wrt_reg_word(volatile __le16 __iomem *addr, u16 data)  in wrt_reg_word()  argument
195 	return writew(data, addr);  in wrt_reg_word()
198 static inline void wrt_reg_dword(volatile __le32 __iomem *addr, u32 data)  in wrt_reg_dword()  argument
200 	return writel(data, addr);  in wrt_reg_dword()
234 /* 83XX: Macros defining 8200 AEN Error-levels */
248 /* 83XX: Macros for defining IDC-Control bits */
257 /* 83XX: Macros for defining class in DEV-Partition Info register */
263 /* 83XX: Macros for IDC Lock-Recovery stages */
265 					     * lock-recovery
267 #define IDC_LOCK_RECOVERY_STAGE2	0x2 /* Stage2: Perform lock-recovery */
270 #define IDC_AUDIT_TIMESTAMP		0x0 /* IDC-AUDIT: Record timestamp of
271 					     * dev-state change to NEED-RESET
272 					     * or NEED-QUIESCENT
274 #define IDC_AUDIT_COMPLETION		0x1 /* IDC-AUDIT: Record duration of
275 					     * reset-recovery completion is
288 #define RD_REG_WORD_PIO(addr)		(inw((unsigned long)addr))  argument
289 #define WRT_REG_WORD_PIO(addr, data)	(outw(data, (unsigned long)addr))  argument
299 #define LOOPID_MAP_SIZE		(ha->max_fibre_devices)
326  * There is no correspondence between an N-PORT id and an AL_PA.  Therefore the
327  * valid range of an N-PORT id is 0 through 0x7ef.
367 #define	LOOP_DOWN_RESET			(LOOP_DOWN_TIME - 30)
372 /* ISP request and response entry counts (37-65535) */
425 /* To identify if a srb is of T10-CRC type. @sp => srb_t pointer */
426 #define IS_PROT_IO(sp)	(sp->flags & SRB_CRC_CTX_DSD_VALID)
723 	 * line up with qla_tgt_cmd->cmd_type
779 	 * Call nvme_private->fd->done() and free @sp. Only used by the NVMe
790 #define GET_CMD_SP(sp) (sp->u.scmd.cmd)
793 	(sp->u.scmd.request_sense_length)
795 	(sp->u.scmd.request_sense_length = len)
797 	(sp->u.scmd.request_sense_ptr)
799 	(sp->u.scmd.request_sense_ptr = ptr)
801 	(sp->u.scmd.fw_sense_length)
803 	(sp->u.scmd.fw_sense_length = len)
861 			__le16	req_q_in;	/*  In-Pointer */
862 			__le16	req_q_out;	/*  Out-Pointer */
864 			__le16	rsp_q_in;	/*  In-Pointer */
865 			__le16	rsp_q_out;	/*  Out-Pointer */
1022 	__le32	req_q_in;		/* A0 - Request Queue In-Pointer */
1023 	__le32	req_q_out;		/* A4 - Request Queue Out-Pointer */
1025 	__le32	rsp_q_in;		/* A8 - Response Queue In-Pointer */
1026 	__le32	rsp_q_out;		/* AC - Response Queue Out-Pointer */
1052 	 &(reg)->u.isp2100.mailbox4 : \
1053 	 &(reg)->u.isp2300.req_q_in)
1056 	 &(reg)->u.isp2100.mailbox4 : \
1057 	 &(reg)->u.isp2300.req_q_out)
1060 	 &(reg)->u.isp2100.mailbox5 : \
1061 	 &(reg)->u.isp2300.rsp_q_in)
1064 	 &(reg)->u.isp2100.mailbox5 : \
1065 	 &(reg)->u.isp2300.rsp_q_out)
1067 #define ISP_ATIO_Q_IN(vha) (vha->hw->tgt.atio_q_in)
1068 #define ISP_ATIO_Q_OUT(vha) (vha->hw->tgt.atio_q_out)
1073 	  &(reg)->u.isp2100.mailbox0 + (num) : \
1074 	  &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
1075 	 &(reg)->u.isp2300.mailbox0 + (num))
1083 	 &(reg)->fb_cmd_2100 : \
1084 	 &(reg)->u.isp2300.fb_cmd)
1128  * ISP mailbox Self-Test status codes
1163 #define MBA_WAKEUP_THRES	0x8005	/* Request Queue Wake-up. */
1204 #define MBA_DPORT_DIAGNOSTICS	0x8080	/* D-port Diagnostics */
1302 #define MBC_NON_PARTICIPATE		0x43	/* Non-Participating Mode. */
1305 #define MBC_ONLINE_SELF_TEST		0x46	/* Online self-test. */
1356 #define MBC_PORT_PARAMS			0x1A	/* Port iDMA Parameters. */
1363 #define MBC_DPORT_DIAGNOSTICS		0x47	/* D-Port Diagnostics */
1505 						/* Bits 15-0 of word 0 */
1507 						/* Bits 15-0 of word 3 */
1546 	 * LSB BIT 2  = Enable Full-Duplex
1618 	 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1619 	 * LSB BIT 6 = Enable Out-of-Order frame handling
1622 	 * MSB BIT 0 = Sbus enable - 2300
1641 	 * BIT 15-14 = Reserved
1642 	 * BIT_13 = SAN Congestion Management (1 - Enabled, 0 - Disabled)
1643 	 * BIT_12 = Remote Write Optimization (1 - Enabled, 0 - Disabled)
1644 	 * BIT 11-0 = Reserved
1733 	 * LSB BIT 2  = Enable Full-Duplex
1792 	 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1793 	 * LSB BIT 6 = Enable Out-of-Order frame handling
1796 	 * MSB BIT 0 = Sbus enable - 2300
1884 	 * BIT 1 = Alt-Boot Enable
1915 	/* Offset 200-215 : Model Number */
1922 	 * NVRAM Adapter Features offset 232-239
1957  * ISP queue - response queue entry definition.
1971  * ISP queue - ATIO queue entry definition.
1999  * ISP queue - command entry structure definition.
2028  * ISP queue - 64-Bit addressing, command entry structure definition.
2049  * ISP queue - continuation entry structure definition.
2062  * ISP queue - 64-Bit addressing, continuation entry structure definition.
2093  * ISP queue - 64-Bit addressing, continuation crc entry structure definition.
2148  * ISP queue - status entry structure definition.
2185 #define SS_MASK				0xfff	/* Reserved bits BIT_12-BIT_15*/
2245  * ISP queue - status continuation entry structure definition.
2257  * ISP queue -	RIO Type 1 status entry (32 bit I/O entry handles)
2270  * ISP queue -	RIO Type 2 status entry (16 bit I/O entry handles)
2283  * ISP queue - marker entry structure definition.
2293 	uint8_t modifier;		/* Modifier (7-0). */
2307  * ISP queue - Management Server entry structure definition.
2338  * ISP queue - Mailbox Command entry structure definition.
2381  * ISP queue -	immediate notify entry structure definition.
2433 					/* PRLI word 3 bit 0-15 */
2478 /* FCP-4 types */
2776  * FC-CT interface
2778  * NOTE: All structures are big-endian in form.
3013 	(sizeof((obj)->type) + sizeof((obj)->len))
3016 	(4 - ((len) & 3))
3049 /* CT command header -- request/response common fields */
3332  * SNS command structures -- for 2200 compatibility.
3396 	uint8_t	loop_id_2100;	/* ISP2100/ISP2200 -- 4 bytes. */
3397 	__le16	loop_id;	/* ISP23XX         -- 6 bytes. */
3398 	uint16_t reserved_1;	/* ISP24XX         -- 8 bytes. */
3420 /* NPIV - return codes of VP create and modify */
3496 /* MSI-X Support *************************************************************/
3682 	((ha->mqenable || IS_QLA83XX(ha) || \
3684 	 ((void __iomem *)ha->mqiobase + (QLA_QUE_PAGE * id)) :\
3685 	 ((void __iomem *)ha->iobase))
3720 	__le32	__iomem *rsp_q_in;	/* FWI2-capable only. */
3747 	__le32	__iomem *req_q_in;	/* FWI2-capable only. */
3821 	 * ha->flags.eeh_busy
3822 	 * ha->flags.pci_channel_io_perm_failure
3823 	 * base_vha->loop_state
3826 	/* move vha->flags.difdix_supported here */
3852 	struct qla_msix_entry *msix; /* point to &ha->msix_entries[x] */
3857 	struct list_head qp_list_elem; /* vha->qp_list */
3996 	(sizeof(obj) - sizeof((obj).desc_tag) - sizeof((obj).desc_len))
4058 	((ha->cur_fw_xcb_count/100) * Q_FULL_THRESH_HOLD_PERCENT)
4307 #define DT_MASK(ha)     ((ha)->isp_type & (DT_ISP_LAST - 1))
4355 #define IS_NOPOLLING_TYPE(ha)	(IS_QLA81XX(ha) && (ha)->flags.msix_enabled)
4362 #define IS_T10_PI_CAPABLE(ha)   ((ha)->device_type & DT_T10_PI)
4363 #define IS_IIDMA_CAPABLE(ha)    ((ha)->device_type & DT_IIDMA)
4364 #define IS_FWI2_CAPABLE(ha)     ((ha)->device_type & DT_FWI2)
4365 #define IS_ZIO_SUPPORTED(ha)    ((ha)->device_type & DT_ZIO_SUPPORTED)
4366 #define IS_OEM_001(ha)          ((ha)->device_type & DT_OEM_001)
4367 #define HAS_EXTENDED_IDS(ha)    ((ha)->device_type & DT_EXTENDED_IDS)
4368 #define IS_CT6_SUPPORTED(ha)	((ha)->device_type & DT_CT6_SUPPORTED)
4375 				((ha)->fw_attributes_ext[0] & BIT_0))
4376 #define QLA_ABTS_FW_ENABLED(_ha)       ((_ha)->fw_attributes_ext[0] & BIT_14)
4377 #define QLA_SRB_NVME_LS(_sp) ((_sp)->type == SRB_NVME_LS)
4378 #define QLA_SRB_NVME_CMD(_sp) ((_sp)->type == SRB_NVME_CMD)
4381 	(QLA_SRB_NVME_LS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4383 	(QLA_SRB_NVME_CMD(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4385 	(QLA_NVME_IOS(_sp) && QLA_ABTS_FW_ENABLED(_sp->fcport->vha->hw))
4395     (((ha)->fw_attributes_h << 16 | (ha)->fw_attributes) & BIT_22))
4398 #define IS_TGT_MODE_CAPABLE(ha)	(ha->tgt.atio_q_length)
4414 	 (ha->zio_mode == QLA_ZIO_MODE_6))
4477 	/* Small DMA pool allocations -- maximum 256 bytes in length. */
4532 	struct mutex mq_lock;        /* multi-queue synchronization */
4784 	/* DPC low-priority workqueue */
4787 	/* DPC high-priority workqueue */
4871 	(ha->fw_ability_mask & FW_ABILITY_MAX_SPEED_MASK)
5179 	_ha->flags.fw_started = 1;		\
5180 	_ha->base_qpair->fw_started = 1;	\
5181 	for (i = 0; i < _ha->max_qpairs; i++) {	\
5182 	if (_ha->queue_pair_map[i])	\
5183 	_ha->queue_pair_map[i]->fw_started = 1;	\
5189 	_ha->flags.fw_started = 0;		\
5190 	_ha->base_qpair->fw_started = 0;	\
5191 	for (i = 0; i < _ha->max_qpairs; i++) {	\
5192 	if (_ha->queue_pair_map[i])	\
5193 	_ha->queue_pair_map[i]->fw_started = 0;	\
5219 	(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5220 	 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
5221 	 atomic_read(&ha->loop_state) == LOOP_DOWN)
5224 		(test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
5225 			 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
5229 	atomic_inc(&vha->vref_count);  in qla_vha_mark_busy()
5231 	if (vha->flags.delete_progress) {  in qla_vha_mark_busy()
5232 		atomic_dec(&vha->vref_count);  in qla_vha_mark_busy()
5233 		wake_up(&vha->vref_waitq);  in qla_vha_mark_busy()
5240 	atomic_dec(&__vha->vref_count);			\
5241 	wake_up(&__vha->vref_waitq);			\
5245 	atomic_inc(&__qpair->ref_count);		\
5247 	if (__qpair->delete_in_progress) {		\
5248 		atomic_dec(&__qpair->ref_count);	\
5256 	atomic_dec(&__qpair->ref_count)
5260     _ha->base_qpair->enable_explicit_conf = 1;	\
5261     for (i = 0; i < _ha->max_qpairs; i++) {	\
5262 	if (_ha->queue_pair_map[i])		\
5263 	    _ha->queue_pair_map[i]->enable_explicit_conf = 1; \
5269     _ha->base_qpair->enable_explicit_conf = 0;	\
5270     for (i = 0; i < _ha->max_qpairs; i++) {	\
5271 	if (_ha->queue_pair_map[i])		\
5272 	    _ha->queue_pair_map[i]->enable_explicit_conf = 0; \
5447 /* BPM -- Buffer Plus Management support. */
5454 	(ql2xautodetectsfp && !vha->vp_idx && IS_BPM_CAPABLE(vha->hw))
5462 	if (_ha->current_topology)				\
5463 		_ha->prev_topology = _ha->current_topology;     \
5467 	((ha->prev_topology == ISP_CFG_N && !ha->current_topology) || \
5468 	 ha->current_topology == ISP_CFG_N || \
5469 	 !ha->current_topology)
5474 	(fcport->fc4_type & FS_FC4TYPE_NVME) \
5477 	(fcport->fc4_type & FS_FC4TYPE_FCP) \
5487 	 (ha->fc4_type_priority == FC4_PRIORITY_NVME))
5490 	(fcport->do_prli_nvme || \
5560 #define IS_SESSION_DELETED(_fcport) (_fcport->disc_state == DSC_DELETE_PEND || \
5561 				      _fcport->disc_state == DSC_DELETED)
5565 	__func__, _fp->port_name, ##_args, atomic_read(&_fp->state), \
5566 	_fp->disc_state, _fp->scan_state, _fp->loop_id, _fp->deleted, \
5567 	_fp->flags
5570 	(!_fcport || IS_SESSION_DELETED(_fcport) || atomic_read(&_fcport->state) != FCS_ONLINE || \
5571 	!_fcport->vha->hw->flags.fw_started)