138 		wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);  in qla27xx_dump_mpi_ram()
157 				wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);  in qla27xx_dump_mpi_ram()
158 				rd_reg_dword(&reg->hccr);  in qla27xx_dump_mpi_ram()
164 			wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);  in qla27xx_dump_mpi_ram()
165 			rd_reg_dword(&reg->hccr);  in qla27xx_dump_mpi_ram()
224 		wrt_reg_dword(&reg->hccr, HCCRX_SET_HOST_INT);  in qla24xx_dump_ram()
240 				wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);  in qla24xx_dump_ram()
241 				rd_reg_dword(&reg->hccr);  in qla24xx_dump_ram()
247 			wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_INT);  in qla24xx_dump_ram()
248 			rd_reg_dword(&reg->hccr);  in qla24xx_dump_ram()
312 	wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_PAUSE);  in qla24xx_pause_risc()
360 	wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);  in qla24xx_soft_reset()
361 	rd_reg_dword(&reg->hccr);             /* PCI Posting. */  in qla24xx_soft_reset()
408 		wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);  in qla2xxx_dump_ram()
424 					wrt_reg_word(&reg->hccr,  in qla2xxx_dump_ram()
426 					rd_reg_word(&reg->hccr);  in qla2xxx_dump_ram()
434 					wrt_reg_word(&reg->hccr,  in qla2xxx_dump_ram()
436 					rd_reg_word(&reg->hccr);  in qla2xxx_dump_ram()
441 				wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);  in qla2xxx_dump_ram()
442 				rd_reg_word(&reg->hccr);  in qla2xxx_dump_ram()
770 	fw->hccr = htons(rd_reg_word(&reg->hccr));  in qla2300_fw_dump()
773 	wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);  in qla2300_fw_dump()
776 		    (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&  in qla2300_fw_dump()
784 		rd_reg_word(&reg->hccr);		/* PCI Posting. */  in qla2300_fw_dump()
926 	fw->hccr = htons(rd_reg_word(&reg->hccr));  in qla2100_fw_dump()
929 	wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);  in qla2100_fw_dump()
930 	for (cnt = 30000; (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&  in qla2100_fw_dump()
1008 		wrt_reg_word(&reg->hccr, HCCR_PAUSE_RISC);  in qla2100_fw_dump()
1010 		    (rd_reg_word(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&  in qla2100_fw_dump()
1026 			wrt_reg_word(&reg->hccr, HCCR_RELEASE_RISC);  in qla2100_fw_dump()
1039 		wrt_reg_word(&reg->hccr, HCCR_SET_HOST_INT);  in qla2100_fw_dump()
1052 					wrt_reg_word(&reg->hccr,  in qla2100_fw_dump()
1054 					rd_reg_word(&reg->hccr);  in qla2100_fw_dump()
1057 				wrt_reg_word(&reg->hccr, HCCR_CLR_RISC_INT);  in qla2100_fw_dump()
1058 				rd_reg_word(&reg->hccr);  in qla2100_fw_dump()
2400 		wrt_reg_dword(&reg->hccr, HCCRX_SET_RISC_RESET);  in qla83xx_fw_dump()
2401 		rd_reg_dword(&reg->hccr);  in qla83xx_fw_dump()
2403 		wrt_reg_dword(&reg->hccr, HCCRX_REL_RISC_PAUSE);  in qla83xx_fw_dump()
2404 		rd_reg_dword(&reg->hccr);  in qla83xx_fw_dump()
2406 		wrt_reg_dword(&reg->hccr, HCCRX_CLR_RISC_RESET);  in qla83xx_fw_dump()
2407 		rd_reg_dword(&reg->hccr);  in qla83xx_fw_dump()