Lines Matching +full:0 +full:x8007
17 #define BIT_0 0x1
18 #define BIT_1 0x2
19 #define BIT_2 0x4
20 #define BIT_3 0x8
21 #define BIT_4 0x10
22 #define BIT_5 0x20
23 #define BIT_6 0x40
24 #define BIT_7 0x80
25 #define BIT_8 0x100
26 #define BIT_9 0x200
27 #define BIT_10 0x400
28 #define BIT_11 0x800
29 #define BIT_12 0x1000
30 #define BIT_13 0x2000
31 #define BIT_14 0x4000
32 #define BIT_15 0x8000
33 #define BIT_16 0x10000
34 #define BIT_17 0x20000
35 #define BIT_18 0x40000
36 #define BIT_19 0x80000
37 #define BIT_20 0x100000
38 #define BIT_21 0x200000
39 #define BIT_22 0x400000
40 #define BIT_23 0x800000
41 #define BIT_24 0x1000000
42 #define BIT_25 0x2000000
43 #define BIT_26 0x4000000
44 #define BIT_27 0x8000000
45 #define BIT_28 0x10000000
46 #define BIT_29 0x20000000
47 #define BIT_30 0x40000000
48 #define BIT_31 0x80000000
77 /* Command retry count (0-65535) */
106 #define SRB_TIMEOUT (1 << 0) /* Command timed out */
117 uint16_t cfg_0; /* Configuration 0 */
118 #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */
144 #define NV_DESELECT 0
152 uint16_t unused_1[0x06];
159 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
170 uint16_t unused_2[0x06];
176 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */
187 uint16_t unused_3[0x0e];
189 uint16_t mailbox0; /* Mailbox 0 */
198 uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
204 uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
209 uint16_t unused_6[0x11]; /* d0-f0 */
218 #define PROD_ID_1 0x4953
219 #define PROD_ID_2 0x0000
220 #define PROD_ID_2a 0x5020
221 #define PROD_ID_3 0x2020
222 #define PROD_ID_4 0x1
227 #define HC_RESET_RISC 0x1000 /* Reset RISC */
228 #define HC_PAUSE_RISC 0x2000 /* Pause RISC */
229 #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */
230 #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */
231 #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
232 #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
233 #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */
238 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
246 #define MBS_CMD_CMP 0x4000 /* Command Complete. */
247 #define MBS_INV_CMD 0x4001 /* Invalid Command. */
248 #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */
249 #define MBS_TEST_FAILED 0x4003 /* Test Failed. */
250 #define MBS_CMD_ERR 0x4005 /* Command Error. */
251 #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */
256 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
257 #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */
258 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
259 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
260 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
261 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
262 #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */
263 #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */
264 #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */
265 #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */
270 #define MBC_NOP 0 /* No Operation */
280 #define MBC_DUMP_RAM_A64_ROM 0x0a /* Dump RAM 64bit ROM version */
281 #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */
282 #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */
283 #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */
284 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */
285 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */
286 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */
287 #define MBC_BUS_RESET 0x18 /* SCSI bus reset */
288 #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */
289 #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */
290 #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */
291 #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */
292 #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */
293 #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */
294 #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */
295 #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */
296 #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */
297 #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */
298 #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */
299 #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */
300 #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */
301 #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */
302 #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */
303 #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */
304 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */
305 #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */
306 #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */
335 uint8_t id0; /* 0 */
379 * 0 = Disable, 1 = high only, 3 = Auto term
521 __le32 dseg_0_address; /* Data segment 0 address. */
522 __le32 dseg_0_length; /* Data segment 0 length. */
541 __le32 dseg_0_address; /* Data segment 0 address. */
542 __le32 dseg_0_length; /* Data segment 0 length. */
601 uint8_t modifier; /* Modifier (7-0). */
602 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
649 __le32 dseg_0_address[2]; /* Data segment 0 address. */
650 __le32 dseg_0_length; /* Data segment 0 length. */
660 #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */
664 __le32 dseg_0_address[2]; /* Data segment 0 address. */
665 __le32 dseg_0_length; /* Data segment 0 length. */
681 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
698 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
709 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
725 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
734 #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */
760 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
820 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
822 __le32 dseg_0_address; /* Data segment 0 address. */
823 __le32 dseg_0_length; /* Data segment 0 length. */
853 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
855 __le32 dseg_0_address; /* Data segment 0 address. */
856 __le32 dseg_0_length; /* Data segment 0 length. */
867 #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */
883 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
886 __le32 dseg_0_address[2];/* Data segment 0 address. */
887 __le32 dseg_0_length; /* Data segment 0 length. */
897 #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */
913 __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */
928 #define CS_COMPLETE 0x0 /* No errors */
929 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
930 #define CS_DMA 0x2 /* A DMA direction error. */
931 #define CS_TRANSPORT 0x3 /* Transport error. */
932 #define CS_RESET 0x4 /* SCSI bus reset occurred */
933 #define CS_ABORTED 0x5 /* System aborted command. */
934 #define CS_TIMEOUT 0x6 /* Timeout error. */
935 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
936 #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */
937 #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */
938 #define CS_BAD_MSG 0xA /* Bad msg after status phase. */
939 #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */
940 #define CS_EXTENDED_ID 0xC /* Extended ID failed. */
941 #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */
942 #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */
943 #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */
944 #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */
945 #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */
946 #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */
947 #define CS_ID_MSG 0x13 /* Target rejected ID msg. */
948 #define CS_FREE 0x14 /* Unexpected bus free. */
949 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
950 #define CS_TRANACTION_1 0x18 /* Transaction error 1 */
951 #define CS_TRANACTION_2 0x19 /* Transaction error 2 */
952 #define CS_TRANACTION_3 0x1a /* Transaction error 3 */
953 #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */
954 #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */
955 #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */
956 #define CS_ARS_FAILED 0x1e /* ARS failed */
957 #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */
958 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
959 #define CS_UNKNOWN 0x81 /* Driver defined */
960 #define CS_RETRY 0x82 /* Driver defined */
1053 uint32_t online:1; /* 0 */