Lines Matching refs:RD_REG_WORD
728 ha->mailbox_out[0] = RD_REG_WORD(®->mailbox0); in qla1280_mailbox_timeout()
731 RD_REG_WORD(®->ictrl), RD_REG_WORD(®->istatus)); in qla1280_mailbox_timeout()
829 RD_REG_WORD(&ha->iobase->istatus)); in qla1280_error_action()
832 RD_REG_WORD(&ha->iobase->host_cmd), in qla1280_error_action()
833 RD_REG_WORD(&ha->iobase->ictrl), jiffies); in qla1280_error_action()
1055 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_disable_intrs()
1063 RD_REG_WORD(&ha->iobase->ictrl); /* PCI Posted Write flush */ in qla1280_enable_intrs()
1424 RD_REG_WORD(®->host_cmd); in qla1280_initialize_adapter()
1573 data = RD_REG_WORD(®->ictrl); in qla1280_chip_diag()
1589 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_chip_diag()
1597 data = RD_REG_WORD(®->mailbox0); in qla1280_chip_diag()
1606 if (RD_REG_WORD(®->mailbox1) != PROD_ID_1 || in qla1280_chip_diag()
1607 (RD_REG_WORD(®->mailbox2) != PROD_ID_2 && in qla1280_chip_diag()
1608 RD_REG_WORD(®->mailbox2) != PROD_ID_2a) || in qla1280_chip_diag()
1609 RD_REG_WORD(®->mailbox3) != PROD_ID_3 || in qla1280_chip_diag()
1610 RD_REG_WORD(®->mailbox4) != PROD_ID_4) { in qla1280_chip_diag()
1613 RD_REG_WORD(®->mailbox1), in qla1280_chip_diag()
1614 RD_REG_WORD(®->mailbox2), in qla1280_chip_diag()
1615 RD_REG_WORD(®->mailbox3), in qla1280_chip_diag()
1616 RD_REG_WORD(®->mailbox4)); in qla1280_chip_diag()
2181 hwrev = RD_REG_WORD(®->cfg_0) & ISP_CFG0_HWMSK; in qla1280_nvram_config()
2183 cfg1 = RD_REG_WORD(®->cfg_1) & ~(BIT_4 | BIT_5 | BIT_6); in qla1280_nvram_config()
2184 cdma_conf = RD_REG_WORD(®->cdma_cfg); in qla1280_nvram_config()
2212 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2215 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_config()
2361 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2364 reg_data = RD_REG_WORD(®->nvram); in qla1280_nvram_request()
2368 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2375 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nvram_request()
2387 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2390 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2393 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_nv_write()
2468 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus)); in qla1280_mailbox_command()
2470 RD_REG_WORD(®->mailbox0), RD_REG_WORD(®->mailbox1), in qla1280_mailbox_command()
2471 RD_REG_WORD(®->mailbox2), RD_REG_WORD(®->mailbox3)); in qla1280_mailbox_command()
2473 RD_REG_WORD(®->mailbox4), RD_REG_WORD(®->mailbox5), in qla1280_mailbox_command()
2474 RD_REG_WORD(®->mailbox6), RD_REG_WORD(®->mailbox7)); in qla1280_mailbox_command()
2511 data = RD_REG_WORD(®->istatus); in qla1280_poll()
2681 RD_REG_WORD(®->id_l); /* Flush PCI write */ in qla1280_reset_adapter()
2765 cnt = RD_REG_WORD(®->mailbox4); in qla1280_64bit_start_scsi()
3027 cnt = RD_REG_WORD(®->mailbox4); in qla1280_32bit_start_scsi()
3244 cnt = RD_REG_WORD(®->mailbox4); in qla1280_req_pkt()
3347 istatus = RD_REG_WORD(®->istatus); in qla1280_isr()
3352 mailbox[5] = RD_REG_WORD(®->mailbox5); in qla1280_isr()
3363 *wptr++ = RD_REG_WORD(®->mailbox0); in qla1280_isr()
3364 *wptr++ = RD_REG_WORD(®->mailbox1); in qla1280_isr()
3365 *wptr = RD_REG_WORD(®->mailbox2); in qla1280_isr()
3368 *wptr++ = RD_REG_WORD(®->mailbox3); in qla1280_isr()
3369 *wptr++ = RD_REG_WORD(®->mailbox4); in qla1280_isr()
3371 *wptr++ = RD_REG_WORD(®->mailbox6); in qla1280_isr()
3372 *wptr = RD_REG_WORD(®->mailbox7); in qla1280_isr()
3767 RD_REG_WORD(®->id_l); in qla1280_abort_isp()
3831 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3832 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3839 ret = RD_REG_WORD(addr); in qla1280_debounce_register()
3840 ret2 = RD_REG_WORD(addr); in qla1280_debounce_register()
3862 config_reg = RD_REG_WORD(®->cfg_1); in qla1280_check_for_dead_scsi_bus()
3864 scsi_control = RD_REG_WORD(®->scsiControlPins); in qla1280_check_for_dead_scsi_bus()