Lines Matching +full:0 +full:x8006
79 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
80 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
82 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
84 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
85 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
86 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
87 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
88 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
89 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
161 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0; in pm8001_phy_init()
163 sas_phy->tproto = 0; in pm8001_phy_init()
169 sas_phy->frame_rcvd = &phy->frame_rcvd[0]; in pm8001_phy_init()
185 for (i = 0; i < USI_MAX_MEMCNT; i++) { in pm8001_free()
226 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet, in pm8001_init_tasklet()
227 (unsigned long)&(pm8001_ha->irq_vector[0])); in pm8001_init_tasklet()
230 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++) in pm8001_init_tasklet()
245 tasklet_kill(&pm8001_ha->tasklet[0]); in pm8001_kill_tasklet()
249 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++) in pm8001_kill_tasklet()
296 return pm8001_handle_irq(pm8001_ha, 0); in pm8001_interrupt_handler_intx()
310 int i, count = 0, rc = 0; in pm8001_alloc()
333 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in pm8001_alloc()
335 pm8001_ha->port[i].wide_port_phymap = 0; in pm8001_alloc()
336 pm8001_ha->port[i].port_attached = 0; in pm8001_alloc()
337 pm8001_ha->port[i].port_state = 0; in pm8001_alloc()
353 for (i = 0; i < count; i++) { in pm8001_alloc()
383 for (i = 0; i < count; i++) { in pm8001_alloc()
423 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000; in pm8001_alloc()
424 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000; in pm8001_alloc()
425 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000; in pm8001_alloc()
426 for (i = 0; i < pm8001_ha->max_memcnt; i++) { in pm8001_alloc()
435 region->alignment) != 0) { in pm8001_alloc()
448 for (i = 0; i < PM8001_MAX_DEVICES; i++) { in pm8001_alloc()
452 atomic_set(&pm8001_ha->devices[i].running_req, 0); in pm8001_alloc()
455 return 0; in pm8001_alloc()
458 for (i = 0; i < pm8001_ha->max_memcnt; i++) { in pm8001_alloc()
479 u32 logicalBar = 0; in pm8001_ioremap()
483 /* map pci mem (PMC pci base 0-3)*/ in pm8001_ioremap()
484 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) { in pm8001_ioremap()
487 ** bar 0 and 1 - logical BAR0 in pm8001_ioremap()
516 pm8001_ha->io_mem[logicalBar].membase = 0; in pm8001_ioremap()
517 pm8001_ha->io_mem[logicalBar].memsize = 0; in pm8001_ioremap()
522 return 0; in pm8001_ioremap()
552 pm8001_ha->non_fatal_count = 0; in pm8001_pci_alloc()
612 memset(sha, 0x00, sizeof(*sha)); in pm8001_prep_sas_ha_init()
630 return 0; in pm8001_prep_sas_ha_init()
647 int i = 0; in pm8001_post_sas_ha_init()
652 for (i = 0; i < chip_info->n_phy; i++) { in pm8001_post_sas_ha_init()
661 sha->sas_addr = &pm8001_ha->sas_addr[0]; in pm8001_post_sas_ha_init()
684 __be64 dev_sas_addr = cpu_to_be64(0x50010c600047f9d0ULL); in pm8001_init_sas_add()
686 for (i = 0; i < pm8001_ha->chip->n_phy; i++) in pm8001_init_sas_add()
689 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr, in pm8001_init_sas_add()
691 return 0; in pm8001_init_sas_add()
708 if (deviceid == 0x8081 || deviceid == 0x0042) { in pm8001_init_sas_add()
712 payload.minor_function = 0; in pm8001_init_sas_add()
724 payload.offset = 0; in pm8001_init_sas_add()
745 for (i = 0, j = 0; i <= 7; i++, j++) { in pm8001_init_sas_add()
747 if (deviceid == 0x8081) in pm8001_init_sas_add()
749 payload.func_specific[0x704 + i]; in pm8001_init_sas_add()
750 else if (deviceid == 0x0042) in pm8001_init_sas_add()
752 payload.func_specific[0x010 + i]; in pm8001_init_sas_add()
757 payload.func_specific[0x010 + i]; in pm8001_init_sas_add()
760 payload.func_specific[0x804 + i]; in pm8001_init_sas_add()
763 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in pm8001_init_sas_add()
764 if (i && ((i % 4) == 0)) in pm8001_init_sas_add()
773 return 0; in pm8001_init_sas_add()
787 return 0; in pm8001_get_phy_settings_info()
792 payload.offset = 0; in pm8001_get_phy_settings_info()
808 return 0; in pm8001_get_phy_settings_info()
832 phycfg->LaneLosCfg = 0x00000132; in pm8001_get_internal_phy_settings()
833 phycfg->LanePgaCfg1 = 0x00203949; in pm8001_get_internal_phy_settings()
834 phycfg->LanePisoCfg1 = 0x000000FF; in pm8001_get_internal_phy_settings()
835 phycfg->LanePisoCfg2 = 0xFF000001; in pm8001_get_internal_phy_settings()
836 phycfg->LanePisoCfg3 = 0xE7011300; in pm8001_get_internal_phy_settings()
837 phycfg->LanePisoCfg4 = 0x631C40C0; in pm8001_get_internal_phy_settings()
838 phycfg->LanePisoCfg5 = 0xF8102036; in pm8001_get_internal_phy_settings()
839 phycfg->LanePisoCfg6 = 0xF74A1000; in pm8001_get_internal_phy_settings()
840 phycfg->LaneBctCtrl = 0x00FB33F8; in pm8001_get_internal_phy_settings()
852 phycfg->LaneLosCfg = 0x00000132; in pm8001_get_external_phy_settings()
853 phycfg->LanePgaCfg1 = 0x00203949; in pm8001_get_external_phy_settings()
854 phycfg->LanePisoCfg1 = 0x000000FF; in pm8001_get_external_phy_settings()
855 phycfg->LanePisoCfg2 = 0xFF000001; in pm8001_get_external_phy_settings()
856 phycfg->LanePisoCfg3 = 0xE7011300; in pm8001_get_external_phy_settings()
857 phycfg->LanePisoCfg4 = 0x63349140; in pm8001_get_external_phy_settings()
858 phycfg->LanePisoCfg5 = 0xF8102036; in pm8001_get_external_phy_settings()
859 phycfg->LanePisoCfg6 = 0xF80D9300; in pm8001_get_external_phy_settings()
860 phycfg->LaneBctCtrl = 0x00FB33F8; in pm8001_get_external_phy_settings()
872 case 0x0070: /* H1280 - 8 external 0 internal */ in pm8001_get_phy_mask()
873 case 0x0072: /* H12F0 - 16 external 0 internal */ in pm8001_get_phy_mask()
874 *phymask = 0x0000; in pm8001_get_phy_mask()
877 case 0x0071: /* H1208 - 0 external 8 internal */ in pm8001_get_phy_mask()
878 case 0x0073: /* H120F - 0 external 16 internal */ in pm8001_get_phy_mask()
879 *phymask = 0xFFFF; in pm8001_get_phy_mask()
882 case 0x0080: /* H1244 - 4 external 4 internal */ in pm8001_get_phy_mask()
883 *phymask = 0x00F0; in pm8001_get_phy_mask()
886 case 0x0081: /* H1248 - 4 external 8 internal */ in pm8001_get_phy_mask()
887 *phymask = 0x0FF0; in pm8001_get_phy_mask()
890 case 0x0082: /* H1288 - 8 external 8 internal */ in pm8001_get_phy_mask()
891 *phymask = 0xFF00; in pm8001_get_phy_mask()
896 "Unknown subsystem device=0x%.04x\n", in pm8001_get_phy_mask()
910 int phymask = 0; in pm8001_set_phy_settings_ven_117c_12G()
911 int i = 0; in pm8001_set_phy_settings_ven_117c_12G()
913 memset(&phycfg_int, 0, sizeof(phycfg_int)); in pm8001_set_phy_settings_ven_117c_12G()
914 memset(&phycfg_ext, 0, sizeof(phycfg_ext)); in pm8001_set_phy_settings_ven_117c_12G()
920 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in pm8001_set_phy_settings_ven_117c_12G()
933 return 0; in pm8001_set_phy_settings_ven_117c_12G()
944 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */ in pm8001_configure_phy_settings()
945 return 0; in pm8001_configure_phy_settings()
950 case 0: in pm8001_configure_phy_settings()
951 return 0; in pm8001_configure_phy_settings()
973 * Queue index #0 is used always for housekeeping, so don't in pm8001_setup_msix()
985 if (rc < 0) in pm8001_setup_msix()
997 return 0; in pm8001_setup_msix()
1002 u32 i = 0, j = 0; in pm8001_request_msix()
1003 int flag = 0, rc = 0; in pm8001_request_msix()
1016 for (i = 0; i < nr_irqs; i++) { in pm8001_request_msix()
1018 sizeof(pm8001_ha->intr_drvname[0]), in pm8001_request_msix()
1028 for (j = 0; j < i; j++) { in pm8001_request_msix()
1066 return 0; in pm8001_request_irq()
1073 pm8001_ha->irq_vector[0].irq_id = 0; in pm8001_request_irq()
1074 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha; in pm8001_request_irq()
1087 for (i = 0; i < pm8001_ha->number_of_intr; i++) in pm8001_free_irq()
1090 for (i = 0; i < pm8001_ha->number_of_intr; i++) in pm8001_free_irq()
1115 u8 i = 0; in pm8001_pci_probe()
1133 pci_reg |= 0x157; in pm8001_pci_probe()
1197 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); in pm8001_pci_probe()
1223 return 0; in pm8001_pci_probe()
1270 for (i = 0; i < ccb_count; i++) { in pm8001_init_ccb_tag()
1285 return 0; in pm8001_init_ccb_tag()
1302 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); in pm8001_pci_remove()
1309 for (i = 0; i < pm8001_ha->ccb_count; i++) { in pm8001_pci_remove()
1330 * Return: 0 on success, anything else on error.
1345 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); in pm8001_pci_suspend()
1351 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering " in pm8001_pci_suspend()
1354 return 0; in pm8001_pci_suspend()
1361 * Return: 0 on success, anything else on error.
1369 u8 i = 0; in pm8001_pci_resume()
1375 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n", in pm8001_pci_resume()
1392 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF); in pm8001_pci_resume()
1400 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0); in pm8001_pci_resume()
1419 for (i = 0; i < pm8001_ha->chip->n_phy; i++) { in pm8001_pci_resume()
1425 return 0; in pm8001_pci_resume()
1437 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1438 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1439 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1440 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1442 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1443 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1444 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1445 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1446 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1447 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1448 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1449 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1450 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1451 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1452 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1453 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1454 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1455 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1456 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1457 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1458 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1460 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1462 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1464 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1466 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1468 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1470 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1472 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1474 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1476 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1478 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1480 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1482 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1484 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1486 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1488 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1490 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1492 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1494 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1495 { PCI_VENDOR_ID_ATTO, 0x8070,
1496 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1497 { PCI_VENDOR_ID_ATTO, 0x8070,
1498 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1499 { PCI_VENDOR_ID_ATTO, 0x8072,
1500 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1501 { PCI_VENDOR_ID_ATTO, 0x8072,
1502 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1503 { PCI_VENDOR_ID_ATTO, 0x8070,
1504 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1505 { PCI_VENDOR_ID_ATTO, 0x8072,
1506 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1507 { PCI_VENDOR_ID_ATTO, 0x8072,
1508 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1534 pm8001_wq = alloc_workqueue("pm80xx", 0, 0); in pm8001_init()
1538 pm8001_id = 0; in pm8001_init()
1545 return 0; in pm8001_init()