scsi/mvsas/mv_defs.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
7  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 	MVS_TX_RING_SZ		= 1024,	/* TX ring size (12-bit) */
31 	MVS_RX_RING_SZ		= 1024, /* RX ring size (12-bit) */
32 					/* software requires power-of-2
38 	MVS_SLOT_BUF_SZ		= 8192, /* cmd tbl + IU + status + PRD */
44 	MVS_SOC_CAN_QUEUE	= MVS_SOC_SLOTS - 2,
49 	MVS_MAX_PHYS		= 8,	/* max. possible phys */
50 	MVS_MAX_PORTS		= 8,	/* max. possible ports */
53 	MVS_MAX_DEVICES	= 1024,	/* max supported device */
79 	/* MVS_GBL_PORT_TYPE */			/* shl for ports 1-3 */
112 	TX_EN			= (1U << 16),	/* Enable TX */
113 	TX_RING_SZ_MASK		= 0xfff,	/* TX ring size, bits 11:0 */
126 	CINT_PRD_BC		= (1U << 28),	/* PRD BC err for read cmd */
135 						/* shl for ports 1-3 */
143 	/* TX (delivery) ring bits */
173 	MCH_PRD_LEN_SHIFT	= 16,		/* 16-bit PRD table len */
190 	MCH_PASSTHRU		= (1U << 12),	/* pass-through (SSP) */
191 	MCH_FBURST		= (1U << 11),	/* first burst (SSP) */
204 	CCTL_ENDIAN_DATA	= (1U << 3),	/* PRD data */
209 	/* MVS_Px_SER_CTLSTAT (per-phy control) */
216 	/* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
224 	PHYEV_POOF		= (1U << 12),	/* phy ready from 1 -> 0 */
245 	PCS_SELF_CLEAR		= (1U << 5),	/* self-clearing int mode */
247 	PCS_CMD_STOP_ERR	= (1U << 3),	/* cmd stop-on-err enable */
298 	PHYR_SATA_SIG0	= 0x20,	/*port SATA signature FIS(Byte 0-3) */
299 	PHYR_SATA_SIG1	= 0x24,	/*port SATA signature FIS(Byte 4-7) */
300 	PHYR_SATA_SIG2	= 0x28,	/*port SATA signature FIS(Byte 8-11) */
301 	PHYR_SATA_SIG3	= 0x2c,	/*port SATA signature FIS(Byte 12-15) */
328 	CMD_BRST_OOB_DET	= 0x10c, /* burst OOB detect register */
330 	CMD_OOB_BURST	= 0x114, /* OOB burst control register */