14 static void mvs_94xx_detect_porttype(struct mvs_info *mvi, int i)  in mvs_94xx_detect_porttype()  argument
17 	struct mvs_phy *phy = &mvi->phy[i];  in mvs_94xx_detect_porttype()
20 	mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE3);  in mvs_94xx_detect_porttype()
21 	reg = mvs_read_port_vsr_data(mvi, i);  in mvs_94xx_detect_porttype()
35 static void set_phy_tuning(struct mvs_info *mvi, int phy_id,  in set_phy_tuning()  argument
54 	if (mvi->pdev->revision == VANIR_A0_REV)  in set_phy_tuning()
80 		mvs_write_port_vsr_addr(mvi, phy_id, setting_0);  in set_phy_tuning()
81 		tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_tuning()
86 		mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_tuning()
89 		mvs_write_port_vsr_addr(mvi, phy_id, setting_1);  in set_phy_tuning()
90 		tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_tuning()
93 		mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_tuning()
97 static void set_phy_ffe_tuning(struct mvs_info *mvi, int phy_id,  in set_phy_ffe_tuning()  argument
103 	if ((mvi->pdev->revision == VANIR_A0_REV)  in set_phy_ffe_tuning()
104 		|| (mvi->pdev->revision == VANIR_B0_REV))  in set_phy_ffe_tuning()
114 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_FFE_CONTROL);  in set_phy_ffe_tuning()
115 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_ffe_tuning()
123 	mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_ffe_tuning()
129 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);  in set_phy_ffe_tuning()
130 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_ffe_tuning()
135 	mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_ffe_tuning()
142 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_DFE_UPDATE_CRTL);  in set_phy_ffe_tuning()
143 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_ffe_tuning()
148 	mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_ffe_tuning()
154 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_REF_CLOCK_CRTL);  in set_phy_ffe_tuning()
155 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_ffe_tuning()
160 	mvs_write_port_vsr_data(mvi, phy_id, tmp);  in set_phy_ffe_tuning()
164 static void set_phy_rate(struct mvs_info *mvi, int phy_id, u8 rate)  in set_phy_rate()  argument
167 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);  in set_phy_rate()
168 	phy_cfg_tmp.v = mvs_read_port_vsr_data(mvi, phy_id);  in set_phy_rate()
200 	mvs_write_port_vsr_data(mvi, phy_id, phy_cfg.v);  in set_phy_rate()
203 static void mvs_94xx_config_reg_from_hba(struct mvs_info *mvi, int phy_id)  in mvs_94xx_config_reg_from_hba()  argument
206 	temp = (u32)(*(u32 *)&mvi->hba_info_param.phy_tuning[phy_id]);  in mvs_94xx_config_reg_from_hba()
208 		mvi->hba_info_param.phy_tuning[phy_id].trans_emp_amp = 0x6;  in mvs_94xx_config_reg_from_hba()
209 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp = 0x1A;  in mvs_94xx_config_reg_from_hba()
210 		mvi->hba_info_param.phy_tuning[phy_id].trans_amp_adj = 0x3;  in mvs_94xx_config_reg_from_hba()
213 	temp = (u8)(*(u8 *)&mvi->hba_info_param.ffe_ctl[phy_id]);  in mvs_94xx_config_reg_from_hba()
215 		switch (mvi->pdev->revision) {  in mvs_94xx_config_reg_from_hba()
218 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;  in mvs_94xx_config_reg_from_hba()
219 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0x7;  in mvs_94xx_config_reg_from_hba()
225 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_rss_sel = 0x7;  in mvs_94xx_config_reg_from_hba()
226 			mvi->hba_info_param.ffe_ctl[phy_id].ffe_cap_sel = 0xC;  in mvs_94xx_config_reg_from_hba()
231 	temp = (u8)(*(u8 *)&mvi->hba_info_param.phy_rate[phy_id]);  in mvs_94xx_config_reg_from_hba()
234 		mvi->hba_info_param.phy_rate[phy_id] = 0x2;  in mvs_94xx_config_reg_from_hba()
236 	set_phy_tuning(mvi, phy_id,  in mvs_94xx_config_reg_from_hba()
237 		mvi->hba_info_param.phy_tuning[phy_id]);  in mvs_94xx_config_reg_from_hba()
238 	set_phy_ffe_tuning(mvi, phy_id,  in mvs_94xx_config_reg_from_hba()
239 		mvi->hba_info_param.ffe_ctl[phy_id]);  in mvs_94xx_config_reg_from_hba()
240 	set_phy_rate(mvi, phy_id,  in mvs_94xx_config_reg_from_hba()
241 		mvi->hba_info_param.phy_rate[phy_id]);  in mvs_94xx_config_reg_from_hba()
244 static void mvs_94xx_enable_xmt(struct mvs_info *mvi, int phy_id)  in mvs_94xx_enable_xmt()  argument
246 	void __iomem *regs = mvi->regs;  in mvs_94xx_enable_xmt()
254 static void mvs_94xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard)  in mvs_94xx_phy_reset()  argument
259 		mvs_write_port_cfg_addr(mvi, phy_id, PHYR_SATA_CTL);  in mvs_94xx_phy_reset()
260 		tmp = mvs_read_port_cfg_data(mvi, phy_id);  in mvs_94xx_phy_reset()
261 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x20000000);  in mvs_94xx_phy_reset()
262 		mvs_write_port_cfg_data(mvi, phy_id, tmp|0x100000);  in mvs_94xx_phy_reset()
265 	tmp = mvs_read_port_irq_stat(mvi, phy_id);  in mvs_94xx_phy_reset()
267 	mvs_write_port_irq_stat(mvi, phy_id, tmp);  in mvs_94xx_phy_reset()
269 		tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_94xx_phy_reset()
271 		mvs_write_phy_ctl(mvi, phy_id, tmp);  in mvs_94xx_phy_reset()
273 			tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_94xx_phy_reset()
280 		tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_94xx_phy_reset()
282 		mvs_write_phy_ctl(mvi, phy_id, tmp);  in mvs_94xx_phy_reset()
286 static void mvs_94xx_phy_disable(struct mvs_info *mvi, u32 phy_id)  in mvs_94xx_phy_disable()  argument
289 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);  in mvs_94xx_phy_disable()
290 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in mvs_94xx_phy_disable()
291 	mvs_write_port_vsr_data(mvi, phy_id, tmp | 0x00800000);  in mvs_94xx_phy_disable()
294 static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)  in mvs_94xx_phy_enable()  argument
299 	revision = mvi->pdev->revision;  in mvs_94xx_phy_enable()
301 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);  in mvs_94xx_phy_enable()
302 		mvs_write_port_vsr_data(mvi, phy_id, 0x8300ffc1);  in mvs_94xx_phy_enable()
305 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_APP_MEM_CTL);  in mvs_94xx_phy_enable()
306 		mvs_write_port_vsr_data(mvi, phy_id, 0x08001006);  in mvs_94xx_phy_enable()
307 		mvs_write_port_vsr_addr(mvi, phy_id, CMD_HOST_RD_DATA);  in mvs_94xx_phy_enable()
308 		mvs_write_port_vsr_data(mvi, phy_id, 0x0000705f);  in mvs_94xx_phy_enable()
311 	mvs_write_port_vsr_addr(mvi, phy_id, VSR_PHY_MODE2);  in mvs_94xx_phy_enable()
312 	tmp = mvs_read_port_vsr_data(mvi, phy_id);  in mvs_94xx_phy_enable()
314 	mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);  in mvs_94xx_phy_enable()
317 static void mvs_94xx_sgpio_init(struct mvs_info *mvi)  in mvs_94xx_sgpio_init()  argument
319 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_sgpio_init()
326 	mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
329 	mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
338 	mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
343 	mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
351 	mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
354 	mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_sgpio_init()
355 		((mvi->id * 4) + 3) << (8 * 3) |  in mvs_94xx_sgpio_init()
356 		((mvi->id * 4) + 2) << (8 * 2) |  in mvs_94xx_sgpio_init()
357 		((mvi->id * 4) + 1) << (8 * 1) |  in mvs_94xx_sgpio_init()
358 		((mvi->id * 4) + 0) << (8 * 0));  in mvs_94xx_sgpio_init()
362 static int mvs_94xx_init(struct mvs_info *mvi)  in mvs_94xx_init()  argument
364 	void __iomem *regs = mvi->regs;  in mvs_94xx_init()
369 	revision = mvi->pdev->revision;  in mvs_94xx_init()
370 	mvs_show_pcie_usage(mvi);  in mvs_94xx_init()
371 	if (mvi->flags & MVF_FLAG_SOC) {  in mvs_94xx_init()
386 	if (mvi->flags & MVF_FLAG_SOC) {  in mvs_94xx_init()
427 	mvs_phy_hacks(mvi);  in mvs_94xx_init()
430 	tmp = mvs_cr32(mvi, CMD_SAS_CTL1);  in mvs_94xx_init()
436 		mvs_cw32(mvi, CMD_SAS_CTL1, tmp);  in mvs_94xx_init()
446 	mw32(MVS_CMD_LIST_LO, mvi->slot_dma);  in mvs_94xx_init()
447 	mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);  in mvs_94xx_init()
449 	mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);  in mvs_94xx_init()
450 	mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);  in mvs_94xx_init()
453 	mw32(MVS_TX_LO, mvi->tx_dma);  in mvs_94xx_init()
454 	mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);  in mvs_94xx_init()
457 	mw32(MVS_RX_LO, mvi->rx_dma);  in mvs_94xx_init()
458 	mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);  in mvs_94xx_init()
460 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_94xx_init()
461 		mvs_94xx_phy_disable(mvi, i);  in mvs_94xx_init()
463 		mvs_set_sas_addr(mvi, i, CONFIG_ID_FRAME3, CONFIG_ID_FRAME4,  in mvs_94xx_init()
464 						cpu_to_le64(mvi->phy[i].dev_sas_addr));  in mvs_94xx_init()
466 		mvs_94xx_enable_xmt(mvi, i);  in mvs_94xx_init()
467 		mvs_94xx_config_reg_from_hba(mvi, i);  in mvs_94xx_init()
468 		mvs_94xx_phy_enable(mvi, i);  in mvs_94xx_init()
470 		mvs_94xx_phy_reset(mvi, i, PHY_RST_HARD);  in mvs_94xx_init()
472 		mvs_94xx_detect_porttype(mvi, i);  in mvs_94xx_init()
475 	if (mvi->flags & MVF_FLAG_SOC) {  in mvs_94xx_init()
486 	for (i = 0; i < mvi->chip->n_phy; i++) {  in mvs_94xx_init()
488 		tmp = mvs_read_port_irq_stat(mvi, i);  in mvs_94xx_init()
490 		mvs_write_port_irq_stat(mvi, i, tmp);  in mvs_94xx_init()
495 		mvs_write_port_irq_mask(mvi, i, tmp);  in mvs_94xx_init()
498 		mvs_update_phyinfo(mvi, i, 1);  in mvs_94xx_init()
541 	tmp = mvs_cr32(mvi, CMD_LINK_TIMER);  in mvs_94xx_init()
543 	mvs_cw32(mvi, CMD_LINK_TIMER, tmp);  in mvs_94xx_init()
547 	mvs_cw32(mvi, CMD_PL_TIMER, tmp);  in mvs_94xx_init()
550 	tmp = mvs_cr32(mvi, CMD_PORT_LAYER_TIMER1);  in mvs_94xx_init()
552 	mvs_cw32(mvi, CMD_PORT_LAYER_TIMER1, tmp);  in mvs_94xx_init()
556 	tmp = mvs_cr32(mvi, CMD_SL_MODE0);  in mvs_94xx_init()
560 	mvs_cw32(mvi, CMD_SL_MODE0, tmp);  in mvs_94xx_init()
565 	mvs_94xx_sgpio_init(mvi);  in mvs_94xx_init()
570 static int mvs_94xx_ioremap(struct mvs_info *mvi)  in mvs_94xx_ioremap()  argument
572 	if (!mvs_ioremap(mvi, 2, -1)) {  in mvs_94xx_ioremap()
573 		mvi->regs_ex = mvi->regs + 0x10200;  in mvs_94xx_ioremap()
574 		mvi->regs += 0x20000;  in mvs_94xx_ioremap()
575 		if (mvi->id == 1)  in mvs_94xx_ioremap()
576 			mvi->regs += 0x4000;  in mvs_94xx_ioremap()
582 static void mvs_94xx_iounmap(struct mvs_info *mvi)  in mvs_94xx_iounmap()  argument
584 	if (mvi->regs) {  in mvs_94xx_iounmap()
585 		mvi->regs -= 0x20000;  in mvs_94xx_iounmap()
586 		if (mvi->id == 1)  in mvs_94xx_iounmap()
587 			mvi->regs -= 0x4000;  in mvs_94xx_iounmap()
588 		mvs_iounmap(mvi->regs);  in mvs_94xx_iounmap()
592 static void mvs_94xx_interrupt_enable(struct mvs_info *mvi)  in mvs_94xx_interrupt_enable()  argument
594 	void __iomem *regs = mvi->regs_ex;  in mvs_94xx_interrupt_enable()
607 static void mvs_94xx_interrupt_disable(struct mvs_info *mvi)  in mvs_94xx_interrupt_disable()  argument
609 	void __iomem *regs = mvi->regs_ex;  in mvs_94xx_interrupt_disable()
623 static u32 mvs_94xx_isr_status(struct mvs_info *mvi, int irq)  in mvs_94xx_isr_status()  argument
625 	void __iomem *regs = mvi->regs_ex;  in mvs_94xx_isr_status()
627 	if (!(mvi->flags & MVF_FLAG_SOC)) {  in mvs_94xx_isr_status()
636 static irqreturn_t mvs_94xx_isr(struct mvs_info *mvi, int irq, u32 stat)  in mvs_94xx_isr()  argument
638 	void __iomem *regs = mvi->regs;  in mvs_94xx_isr()
640 	if (((stat & MVS_IRQ_SAS_A) && mvi->id == 0) ||  in mvs_94xx_isr()
641 			((stat & MVS_IRQ_SAS_B) && mvi->id == 1)) {  in mvs_94xx_isr()
644 		spin_lock(&mvi->lock);  in mvs_94xx_isr()
645 		mvs_int_full(mvi);  in mvs_94xx_isr()
646 		spin_unlock(&mvi->lock);  in mvs_94xx_isr()
651 static void mvs_94xx_command_active(struct mvs_info *mvi, u32 slot_idx)  in mvs_94xx_command_active()  argument
654 	tmp = mvs_cr32(mvi, MVS_COMMAND_ACTIVE+(slot_idx >> 3));  in mvs_94xx_command_active()
657 		mvs_cw32(mvi, MVS_COMMAND_ACTIVE + (slot_idx >> 3),  in mvs_94xx_command_active()
660 			tmp = mvs_cr32(mvi,  in mvs_94xx_command_active()
667 mvs_94xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all)  in mvs_94xx_clear_srs_irq()  argument
669 	void __iomem *regs = mvi->regs;  in mvs_94xx_clear_srs_irq()
699 static void mvs_94xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type,  in mvs_94xx_issue_stop()  argument
702 	void __iomem *regs = mvi->regs;  in mvs_94xx_issue_stop()
704 	mvs_94xx_clear_srs_irq(mvi, 0, 1);  in mvs_94xx_issue_stop()
712 static void mvs_94xx_non_spec_ncq_error(struct mvs_info *mvi)  in mvs_94xx_non_spec_ncq_error()  argument
714 	void __iomem *regs = mvi->regs;  in mvs_94xx_non_spec_ncq_error()
726 			device = mvs_find_dev_by_reg_set(mvi, i);  in mvs_94xx_non_spec_ncq_error()
728 				mvs_release_task(mvi, device->sas_device);  in mvs_94xx_non_spec_ncq_error()
731 			device = mvs_find_dev_by_reg_set(mvi, i+32);  in mvs_94xx_non_spec_ncq_error()
733 				mvs_release_task(mvi, device->sas_device);  in mvs_94xx_non_spec_ncq_error()
741 static void mvs_94xx_free_reg_set(struct mvs_info *mvi, u8 *tfs)  in mvs_94xx_free_reg_set()  argument
743 	void __iomem *regs = mvi->regs;  in mvs_94xx_free_reg_set()
749 	mvi->sata_reg_set &= ~bit(reg_set);  in mvs_94xx_free_reg_set()
751 		w_reg_set_enable(reg_set, (u32)mvi->sata_reg_set);  in mvs_94xx_free_reg_set()
753 		w_reg_set_enable(reg_set, (u32)(mvi->sata_reg_set >> 32));  in mvs_94xx_free_reg_set()
760 static u8 mvs_94xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs)  in mvs_94xx_assign_reg_set()  argument
763 	void __iomem *regs = mvi->regs;  in mvs_94xx_assign_reg_set()
768 	i = mv_ffc64(mvi->sata_reg_set);  in mvs_94xx_assign_reg_set()
770 		mvi->sata_reg_set |= bit(i);  in mvs_94xx_assign_reg_set()
771 		w_reg_set_enable(i, (u32)(mvi->sata_reg_set >> 32));  in mvs_94xx_assign_reg_set()
775 		mvi->sata_reg_set |= bit(i);  in mvs_94xx_assign_reg_set()
776 		w_reg_set_enable(i, (u32)mvi->sata_reg_set);  in mvs_94xx_assign_reg_set()
798 static int mvs_94xx_oob_done(struct mvs_info *mvi, int i)  in mvs_94xx_oob_done()  argument
801 	phy_st = mvs_read_phy_ctl(mvi, i);  in mvs_94xx_oob_done()
807 static void mvs_94xx_get_dev_identify_frame(struct mvs_info *mvi, int port_id,  in mvs_94xx_get_dev_identify_frame()  argument
814 		mvs_write_port_cfg_addr(mvi, port_id,  in mvs_94xx_get_dev_identify_frame()
816 		id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));  in mvs_94xx_get_dev_identify_frame()
821 static void mvs_94xx_get_att_identify_frame(struct mvs_info *mvi, int port_id,  in mvs_94xx_get_att_identify_frame()  argument
828 		mvs_write_port_cfg_addr(mvi, port_id,  in mvs_94xx_get_att_identify_frame()
830 		id_frame[i] = cpu_to_le32(mvs_read_port_cfg_data(mvi, port_id));  in mvs_94xx_get_att_identify_frame()
832 			port_id + mvi->id * mvi->chip->n_phy, i, id_frame[i]);  in mvs_94xx_get_att_identify_frame()
864 static void mvs_94xx_fix_phy_info(struct mvs_info *mvi, int i,  in mvs_94xx_fix_phy_info()  argument
867 	struct mvs_phy *phy = &mvi->phy[i];  in mvs_94xx_fix_phy_info()
877 	mvs_94xx_get_dev_identify_frame(mvi, i, id);  in mvs_94xx_fix_phy_info()
881 		mvs_94xx_get_att_identify_frame(mvi, i, id);  in mvs_94xx_fix_phy_info()
889 	mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);  in mvs_94xx_fix_phy_info()
890 	mvs_write_port_cfg_data(mvi, i, 0x04);  in mvs_94xx_fix_phy_info()
894 static void mvs_94xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id,  in mvs_94xx_phy_set_link_rate()  argument
900 	tmp = mvs_read_phy_ctl(mvi, phy_id);  in mvs_94xx_phy_set_link_rate()
907 	mvs_write_phy_ctl(mvi, phy_id, tmp);  in mvs_94xx_phy_set_link_rate()
908 	mvs_94xx_phy_reset(mvi, phy_id, PHY_RST_HARD);  in mvs_94xx_phy_set_link_rate()
911 static void mvs_94xx_clear_active_cmds(struct mvs_info *mvi)  in mvs_94xx_clear_active_cmds()  argument
914 	void __iomem *regs = mvi->regs;  in mvs_94xx_clear_active_cmds()
924 static u32 mvs_94xx_spi_read_data(struct mvs_info *mvi)  in mvs_94xx_spi_read_data()  argument
926 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_spi_read_data()
930 static void mvs_94xx_spi_write_data(struct mvs_info *mvi, u32 data)  in mvs_94xx_spi_write_data()  argument
932 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_spi_write_data()
938 static int mvs_94xx_spi_buildcmd(struct mvs_info *mvi,  in mvs_94xx_spi_buildcmd()  argument
946 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_spi_buildcmd()
963 static int mvs_94xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd)  in mvs_94xx_spi_issuecmd()  argument
965 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_spi_issuecmd()
971 static int mvs_94xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout)  in mvs_94xx_spi_waitdataready()  argument
973 	void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_spi_waitdataready()
986 static void mvs_94xx_fix_dma(struct mvs_info *mvi, u32 phy_mask,  in mvs_94xx_fix_dma()  argument
998 	if ((mvi->pdev->revision == VANIR_A0_REV) ||  in mvs_94xx_fix_dma()
999 			(mvi->pdev->revision == VANIR_B0_REV))  in mvs_94xx_fix_dma()
1001 				mvi->bulk_buffer_dma : mvi->bulk_buffer_dma1;  in mvs_94xx_fix_dma()
1018 static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)  in mvs_94xx_tune_interrupt()  argument
1020 	void __iomem *regs = mvi->regs;  in mvs_94xx_tune_interrupt()
1063 			struct mvs_info *mvi = mvs_prv->mvi[i/(4*3)];  in mvs_94xx_gpio_write()  local
1065 			void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_gpio_write()
1070 				MVS_SGPIO_HOST_OFFSET * mvi->id);  in mvs_94xx_gpio_write()
1106 				MVS_SGPIO_HOST_OFFSET * mvi->id);  in mvs_94xx_gpio_write()
1117 			struct mvs_info *mvi = mvs_prv->mvi[i+reg_index];  in mvs_94xx_gpio_write()  local
1118 			void __iomem *regs = mvi->regs_ex - 0x10200;  in mvs_94xx_gpio_write()
1120 			mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,  in mvs_94xx_gpio_write()