Lines Matching full:mvi
14 static void mvs_64xx_detect_porttype(struct mvs_info *mvi, int i) in mvs_64xx_detect_porttype() argument
16 void __iomem *regs = mvi->regs; in mvs_64xx_detect_porttype()
18 struct mvs_phy *phy = &mvi->phy[i]; in mvs_64xx_detect_porttype()
28 static void mvs_64xx_enable_xmt(struct mvs_info *mvi, int phy_id) in mvs_64xx_enable_xmt() argument
30 void __iomem *regs = mvi->regs; in mvs_64xx_enable_xmt()
34 if (mvi->chip->n_phy <= MVS_SOC_PORTS) in mvs_64xx_enable_xmt()
41 static void mvs_64xx_phy_hacks(struct mvs_info *mvi) in mvs_64xx_phy_hacks() argument
43 void __iomem *regs = mvi->regs; in mvs_64xx_phy_hacks()
46 mvs_phy_hacks(mvi); in mvs_64xx_phy_hacks()
48 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_phy_hacks()
50 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE8); in mvs_64xx_phy_hacks()
51 mvs_write_port_vsr_data(mvi, i, 0x2F0); in mvs_64xx_phy_hacks()
56 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_64xx_phy_hacks()
57 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE7); in mvs_64xx_phy_hacks()
58 mvs_write_port_vsr_data(mvi, i, 0x90000000); in mvs_64xx_phy_hacks()
59 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE9); in mvs_64xx_phy_hacks()
60 mvs_write_port_vsr_data(mvi, i, 0x50f2); in mvs_64xx_phy_hacks()
61 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE11); in mvs_64xx_phy_hacks()
62 mvs_write_port_vsr_data(mvi, i, 0x0e); in mvs_64xx_phy_hacks()
67 static void mvs_64xx_stp_reset(struct mvs_info *mvi, u32 phy_id) in mvs_64xx_stp_reset() argument
69 void __iomem *regs = mvi->regs; in mvs_64xx_stp_reset()
72 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_stp_reset()
74 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, ®); in mvs_64xx_stp_reset()
76 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, ®); in mvs_64xx_stp_reset()
87 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_stp_reset()
89 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_stp_reset()
91 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, reg); in mvs_64xx_stp_reset()
93 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_stp_reset()
95 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, reg); in mvs_64xx_stp_reset()
104 static void mvs_64xx_phy_reset(struct mvs_info *mvi, u32 phy_id, int hard) in mvs_64xx_phy_reset() argument
107 tmp = mvs_read_port_irq_stat(mvi, phy_id); in mvs_64xx_phy_reset()
109 mvs_write_port_irq_stat(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
110 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
115 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_reset()
118 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_reset()
124 mvs_64xx_clear_srs_irq(struct mvs_info *mvi, u8 reg_set, u8 clear_all) in mvs_64xx_clear_srs_irq() argument
126 void __iomem *regs = mvi->regs; in mvs_64xx_clear_srs_irq()
144 static int mvs_64xx_chip_reset(struct mvs_info *mvi) in mvs_64xx_chip_reset() argument
146 void __iomem *regs = mvi->regs; in mvs_64xx_chip_reset()
156 if (mvi->flags & MVF_PHY_PWR_FIX) { in mvs_64xx_chip_reset()
157 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_chip_reset()
160 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_chip_reset()
162 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_chip_reset()
165 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_chip_reset()
188 dev_printk(KERN_ERR, mvi->dev, "HBA reset failed\n"); in mvs_64xx_chip_reset()
194 static void mvs_64xx_phy_disable(struct mvs_info *mvi, u32 phy_id) in mvs_64xx_phy_disable() argument
196 void __iomem *regs = mvi->regs; in mvs_64xx_phy_disable()
198 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_phy_disable()
206 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_disable()
208 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_disable()
216 static void mvs_64xx_phy_enable(struct mvs_info *mvi, u32 phy_id) in mvs_64xx_phy_enable() argument
218 void __iomem *regs = mvi->regs; in mvs_64xx_phy_enable()
220 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_phy_enable()
228 pci_read_config_dword(mvi->pdev, offs, &tmp); in mvs_64xx_phy_enable()
230 pci_write_config_dword(mvi->pdev, offs, tmp); in mvs_64xx_phy_enable()
238 static int mvs_64xx_init(struct mvs_info *mvi) in mvs_64xx_init() argument
240 void __iomem *regs = mvi->regs; in mvs_64xx_init()
244 if (mvi->pdev && mvi->pdev->revision == 0) in mvs_64xx_init()
245 mvi->flags |= MVF_PHY_PWR_FIX; in mvs_64xx_init()
246 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_init()
247 mvs_show_pcie_usage(mvi); in mvs_64xx_init()
248 tmp = mvs_64xx_chip_reset(mvi); in mvs_64xx_init()
266 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_init()
268 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp); in mvs_64xx_init()
271 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp); in mvs_64xx_init()
273 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp); in mvs_64xx_init()
276 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp); in mvs_64xx_init()
278 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp); in mvs_64xx_init()
281 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp); in mvs_64xx_init()
298 mvs_64xx_phy_hacks(mvi); in mvs_64xx_init()
300 tmp = mvs_cr32(mvi, CMD_PHY_MODE_21); in mvs_64xx_init()
303 mvs_cw32(mvi, CMD_PHY_MODE_21, tmp); in mvs_64xx_init()
308 mw32(MVS_CMD_LIST_LO, mvi->slot_dma); in mvs_64xx_init()
309 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16); in mvs_64xx_init()
311 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma); in mvs_64xx_init()
312 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16); in mvs_64xx_init()
315 mw32(MVS_TX_LO, mvi->tx_dma); in mvs_64xx_init()
316 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16); in mvs_64xx_init()
319 mw32(MVS_RX_LO, mvi->rx_dma); in mvs_64xx_init()
320 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16); in mvs_64xx_init()
322 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_64xx_init()
325 mvs_set_sas_addr(mvi, i, PHYR_ADDR_LO, PHYR_ADDR_HI, in mvs_64xx_init()
326 cpu_to_be64(mvi->phy[i].dev_sas_addr)); in mvs_64xx_init()
328 mvs_64xx_enable_xmt(mvi, i); in mvs_64xx_init()
330 mvs_64xx_phy_reset(mvi, i, MVS_HARD_RESET); in mvs_64xx_init()
332 mvs_64xx_detect_porttype(mvi, i); in mvs_64xx_init()
334 if (mvi->flags & MVF_FLAG_SOC) { in mvs_64xx_init()
345 for (i = 0; i < mvi->chip->n_phy; i++) { in mvs_64xx_init()
347 tmp = mvs_read_port_irq_stat(mvi, i); in mvs_64xx_init()
349 mvs_write_port_irq_stat(mvi, i, tmp); in mvs_64xx_init()
355 mvs_write_port_irq_mask(mvi, i, tmp); in mvs_64xx_init()
358 mvs_update_phyinfo(mvi, i, 1); in mvs_64xx_init()
407 static int mvs_64xx_ioremap(struct mvs_info *mvi) in mvs_64xx_ioremap() argument
409 if (!mvs_ioremap(mvi, 4, 2)) in mvs_64xx_ioremap()
414 static void mvs_64xx_iounmap(struct mvs_info *mvi) in mvs_64xx_iounmap() argument
416 mvs_iounmap(mvi->regs); in mvs_64xx_iounmap()
417 mvs_iounmap(mvi->regs_ex); in mvs_64xx_iounmap()
420 static void mvs_64xx_interrupt_enable(struct mvs_info *mvi) in mvs_64xx_interrupt_enable() argument
422 void __iomem *regs = mvi->regs; in mvs_64xx_interrupt_enable()
429 static void mvs_64xx_interrupt_disable(struct mvs_info *mvi) in mvs_64xx_interrupt_disable() argument
431 void __iomem *regs = mvi->regs; in mvs_64xx_interrupt_disable()
438 static u32 mvs_64xx_isr_status(struct mvs_info *mvi, int irq) in mvs_64xx_isr_status() argument
440 void __iomem *regs = mvi->regs; in mvs_64xx_isr_status()
443 if (!(mvi->flags & MVF_FLAG_SOC)) { in mvs_64xx_isr_status()
453 static irqreturn_t mvs_64xx_isr(struct mvs_info *mvi, int irq, u32 stat) in mvs_64xx_isr() argument
455 void __iomem *regs = mvi->regs; in mvs_64xx_isr()
460 spin_lock(&mvi->lock); in mvs_64xx_isr()
461 mvs_int_full(mvi); in mvs_64xx_isr()
462 spin_unlock(&mvi->lock); in mvs_64xx_isr()
467 static void mvs_64xx_command_active(struct mvs_info *mvi, u32 slot_idx) in mvs_64xx_command_active() argument
470 mvs_cw32(mvi, 0x40 + (slot_idx >> 3), 1 << (slot_idx % 32)); in mvs_64xx_command_active()
471 mvs_cw32(mvi, 0x00 + (slot_idx >> 3), 1 << (slot_idx % 32)); in mvs_64xx_command_active()
473 tmp = mvs_cr32(mvi, 0x00 + (slot_idx >> 3)); in mvs_64xx_command_active()
476 tmp = mvs_cr32(mvi, 0x40 + (slot_idx >> 3)); in mvs_64xx_command_active()
480 static void mvs_64xx_issue_stop(struct mvs_info *mvi, enum mvs_port_type type, in mvs_64xx_issue_stop() argument
483 void __iomem *regs = mvi->regs; in mvs_64xx_issue_stop()
495 static void mvs_64xx_free_reg_set(struct mvs_info *mvi, u8 *tfs) in mvs_64xx_free_reg_set() argument
497 void __iomem *regs = mvi->regs; in mvs_64xx_free_reg_set()
520 static u8 mvs_64xx_assign_reg_set(struct mvs_info *mvi, u8 *tfs) in mvs_64xx_assign_reg_set() argument
524 void __iomem *regs = mvi->regs; in mvs_64xx_assign_reg_set()
531 for (i = 0; i < mvi->chip->srs_sz; i++) { in mvs_64xx_assign_reg_set()
563 static int mvs_64xx_oob_done(struct mvs_info *mvi, int i) in mvs_64xx_oob_done() argument
566 mvs_write_port_cfg_addr(mvi, i, in mvs_64xx_oob_done()
568 phy_st = mvs_read_port_cfg_data(mvi, i); in mvs_64xx_oob_done()
574 static void mvs_64xx_fix_phy_info(struct mvs_info *mvi, int i, in mvs_64xx_fix_phy_info() argument
578 struct mvs_phy *phy = &mvi->phy[i]; in mvs_64xx_fix_phy_info()
592 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY); in mvs_64xx_fix_phy_info()
593 phy->dev_info = mvs_read_port_cfg_data(mvi, i); in mvs_64xx_fix_phy_info()
595 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO); in mvs_64xx_fix_phy_info()
596 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i); in mvs_64xx_fix_phy_info()
598 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI); in mvs_64xx_fix_phy_info()
600 (u64) mvs_read_port_cfg_data(mvi, i) << 32; in mvs_64xx_fix_phy_info()
601 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO); in mvs_64xx_fix_phy_info()
602 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i); in mvs_64xx_fix_phy_info()
606 static void mvs_64xx_phy_work_around(struct mvs_info *mvi, int i) in mvs_64xx_phy_work_around() argument
609 struct mvs_phy *phy = &mvi->phy[i]; in mvs_64xx_phy_work_around()
610 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6); in mvs_64xx_phy_work_around()
611 tmp = mvs_read_port_vsr_data(mvi, i); in mvs_64xx_phy_work_around()
618 mvs_write_port_vsr_data(mvi, i, tmp); in mvs_64xx_phy_work_around()
621 static void mvs_64xx_phy_set_link_rate(struct mvs_info *mvi, u32 phy_id, in mvs_64xx_phy_set_link_rate() argument
627 tmp = mvs_read_phy_ctl(mvi, phy_id); in mvs_64xx_phy_set_link_rate()
639 mvs_write_phy_ctl(mvi, phy_id, tmp); in mvs_64xx_phy_set_link_rate()
640 mvs_64xx_phy_reset(mvi, phy_id, MVS_HARD_RESET); in mvs_64xx_phy_set_link_rate()
643 static void mvs_64xx_clear_active_cmds(struct mvs_info *mvi) in mvs_64xx_clear_active_cmds() argument
646 void __iomem *regs = mvi->regs; in mvs_64xx_clear_active_cmds()
656 static u32 mvs_64xx_spi_read_data(struct mvs_info *mvi) in mvs_64xx_spi_read_data() argument
658 void __iomem *regs = mvi->regs_ex; in mvs_64xx_spi_read_data()
662 static void mvs_64xx_spi_write_data(struct mvs_info *mvi, u32 data) in mvs_64xx_spi_write_data() argument
664 void __iomem *regs = mvi->regs_ex; in mvs_64xx_spi_write_data()
670 static int mvs_64xx_spi_buildcmd(struct mvs_info *mvi, in mvs_64xx_spi_buildcmd() argument
694 static int mvs_64xx_spi_issuecmd(struct mvs_info *mvi, u32 cmd) in mvs_64xx_spi_issuecmd() argument
696 void __iomem *regs = mvi->regs_ex; in mvs_64xx_spi_issuecmd()
709 static int mvs_64xx_spi_waitdataready(struct mvs_info *mvi, u32 timeout) in mvs_64xx_spi_waitdataready() argument
711 void __iomem *regs = mvi->regs_ex; in mvs_64xx_spi_waitdataready()
724 static void mvs_64xx_fix_dma(struct mvs_info *mvi, u32 phy_mask, in mvs_64xx_fix_dma() argument
729 dma_addr_t buf_dma = mvi->bulk_buffer_dma; in mvs_64xx_fix_dma()
739 static void mvs_64xx_tune_interrupt(struct mvs_info *mvi, u32 time) in mvs_64xx_tune_interrupt() argument
741 void __iomem *regs = mvi->regs; in mvs_64xx_tune_interrupt()