Lines Matching +full:0 +full:x000000c8
16 * with MPI v2.0 products. Unless otherwise noted, names beginning with
17 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
28 * Moved ReplyPostHostIndex register to offset 0x6C of the
39 * product specific codes up to 0xEFFF.
41 * and changed the flush value to 0x0.
69 * function codes, 0xF0 to 0xFF.
140 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
142 #define MPI2_VERSION_MINOR_MASK (0x00FF)
143 #define MPI2_VERSION_MINOR_SHIFT (0)
146 #define MPI2_VERSION_MAJOR (0x02)
148 /*minor version for MPI v2.0 compatible products */
149 #define MPI2_VERSION_MINOR (0x00)
152 #define MPI2_VERSION_02_00 (0x0200)
155 #define MPI25_VERSION_MINOR (0x05)
158 #define MPI2_VERSION_02_05 (0x0205)
161 #define MPI26_VERSION_MINOR (0x06)
164 #define MPI2_VERSION_02_06 (0x0206)
168 #define MPI2_HEADER_VERSION_UNIT (0x39)
169 #define MPI2_HEADER_VERSION_DEV (0x00)
170 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
172 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
173 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
183 #define MPI2_IOC_STATE_RESET (0x00000000)
184 #define MPI2_IOC_STATE_READY (0x10000000)
185 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
186 #define MPI2_IOC_STATE_FAULT (0x40000000)
187 #define MPI2_IOC_STATE_COREDUMP (0x50000000)
189 #define MPI2_IOC_STATE_MASK (0xF0000000)
193 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
194 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
203 U32 Doorbell; /*0x00 */
204 U32 WriteSequence; /*0x04 */
205 U32 HostDiagnostic; /*0x08 */
206 U32 Reserved1; /*0x0C */
207 U32 DiagRWData; /*0x10 */
208 U32 DiagRWAddressLow; /*0x14 */
209 U32 DiagRWAddressHigh; /*0x18 */
210 U32 Reserved2[5]; /*0x1C */
211 U32 HostInterruptStatus; /*0x30 */
212 U32 HostInterruptMask; /*0x34 */
213 U32 DCRData; /*0x38 */
214 U32 DCRAddress; /*0x3C */
215 U32 Reserved3[2]; /*0x40 */
216 U32 ReplyFreeHostIndex; /*0x48 */
217 U32 Reserved4[8]; /*0x4C */
218 U32 ReplyPostHostIndex; /*0x6C */
219 U32 Reserved5; /*0x70 */
220 U32 HCBSize; /*0x74 */
221 U32 HCBAddressLow; /*0x78 */
222 U32 HCBAddressHigh; /*0x7C */
223 U32 Reserved6[12]; /*0x80 */
224 U32 Scratchpad[4]; /*0xB0 */
225 U32 RequestDescriptorPostLow; /*0xC0 */
226 U32 RequestDescriptorPostHigh; /*0xC4 */
227 U32 AtomicRequestDescriptorPost;/*0xC8 */
228 U32 Reserved7[13]; /*0xCC */
237 #define MPI2_DOORBELL_OFFSET (0x00000000)
240 #define MPI2_DOORBELL_USED (0x08000000)
241 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
243 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
244 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
247 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
249 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
255 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
256 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
257 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
258 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
259 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
260 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
261 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
262 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
263 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
268 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
270 #define MPI26_DIAG_SECURE_BOOT (0x80000000)
272 #define MPI2_DIAG_SBR_RELOAD (0x00002000)
274 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
275 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
276 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
279 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000)
280 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800)
281 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000)
282 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800)
284 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
285 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
286 #define MPI2_DIAG_HCB_MODE (0x00000100)
287 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
288 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
289 #define MPI2_DIAG_RESET_HISTORY (0x00000020)
290 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
291 #define MPI2_DIAG_RESET_ADAPTER (0x00000004)
292 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
297 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
298 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
299 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
304 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
305 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
307 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
308 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
309 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
315 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
316 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
317 #define MPI2_HIM_REPLY_INT_MASK (0x00000008)
319 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
325 #define MPI2_DCR_DATA_OFFSET (0x00000038)
326 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
331 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
336 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
337 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
338 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
340 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /*MPI v2.5 only*/
346 #define MPI2_HCB_SIZE_OFFSET (0x00000074)
347 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
348 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
350 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
351 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
356 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0)
357 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4)
358 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8)
359 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC)
364 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
365 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
366 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8)
383 U8 RequestFlags; /*0x00 */
384 U8 MSIxIndex; /*0x01 */
385 U16 SMID; /*0x02 */
386 U16 LMID; /*0x04 */
387 U16 DescriptorTypeDependent; /*0x06 */
394 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E)
396 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
397 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
398 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
399 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
400 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
401 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
402 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10)
404 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
408 U8 RequestFlags; /*0x00 */
409 U8 MSIxIndex; /*0x01 */
410 U16 SMID; /*0x02 */
411 U16 LMID; /*0x04 */
412 U16 Reserved1; /*0x06 */
420 U8 RequestFlags; /*0x00 */
421 U8 MSIxIndex; /*0x01 */
422 U16 SMID; /*0x02 */
423 U16 LMID; /*0x04 */
424 U16 DevHandle; /*0x06 */
432 U8 RequestFlags; /*0x00 */
433 U8 MSIxIndex; /*0x01 */
434 U16 SMID; /*0x02 */
435 U16 LMID; /*0x04 */
436 U16 IoIndex; /*0x06 */
444 U8 RequestFlags; /*0x00 */
445 U8 MSIxIndex; /*0x01 */
446 U16 SMID; /*0x02 */
447 U16 LMID; /*0x04 */
448 U16 Reserved; /*0x06 */
499 U8 RequestFlags; /* 0x00 */
500 U8 MSIxIndex; /* 0x01 */
501 U16 SMID; /* 0x02 */
515 U8 ReplyFlags; /*0x00 */
516 U8 MSIxIndex; /*0x01 */
517 U16 DescriptorTypeDependent1; /*0x02 */
518 U32 DescriptorTypeDependent2; /*0x04 */
525 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
526 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
527 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
528 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
529 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
530 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
531 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
532 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08)
533 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
536 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
537 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
541 U8 ReplyFlags; /*0x00 */
542 U8 MSIxIndex; /*0x01 */
543 U16 SMID; /*0x02 */
544 U32 ReplyFrameAddress; /*0x04 */
550 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
554 U8 ReplyFlags; /*0x00 */
555 U8 MSIxIndex; /*0x01 */
556 U16 SMID; /*0x02 */
557 U16 TaskTag; /*0x04 */
558 U16 Reserved1; /*0x06 */
566 U8 ReplyFlags; /*0x00 */
567 U8 MSIxIndex; /*0x01 */
568 U16 SMID; /*0x02 */
569 U8 SequenceNumber; /*0x04 */
570 U8 Reserved1; /*0x05 */
571 U16 IoIndex; /*0x06 */
579 U8 ReplyFlags; /*0x00 */
580 U8 MSIxIndex; /*0x01 */
581 U8 VP_ID; /*0x02 */
582 U8 Flags; /*0x03 */
583 U16 InitiatorDevHandle; /*0x04 */
584 U16 IoIndex; /*0x06 */
591 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
595 U8 ReplyFlags; /*0x00 */
596 U8 MSIxIndex; /*0x01 */
597 U16 SMID; /*0x02 */
598 U32 Reserved; /*0x04 */
641 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
642 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
643 #define MPI2_FUNCTION_IOC_INIT (0x02)
644 #define MPI2_FUNCTION_IOC_FACTS (0x03)
645 #define MPI2_FUNCTION_CONFIG (0x04)
646 #define MPI2_FUNCTION_PORT_FACTS (0x05)
647 #define MPI2_FUNCTION_PORT_ENABLE (0x06)
648 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
649 #define MPI2_FUNCTION_EVENT_ACK (0x08)
650 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
651 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
652 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
653 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
654 #define MPI2_FUNCTION_FW_UPLOAD (0x12)
655 #define MPI2_FUNCTION_RAID_ACTION (0x15)
656 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
657 #define MPI2_FUNCTION_TOOLBOX (0x17)
658 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
659 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
660 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
661 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B)
662 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
663 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
664 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
665 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
666 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
667 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
668 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
669 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
670 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
671 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33)
672 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
673 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
676 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
677 #define MPI2_FUNCTION_HANDSHAKE (0x42)
686 #define MPI2_IOCSTATUS_MASK (0x7FFF)
692 #define MPI2_IOCSTATUS_SUCCESS (0x0000)
693 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
694 #define MPI2_IOCSTATUS_BUSY (0x0002)
695 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
696 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
697 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
698 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
699 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
700 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
701 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
703 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
704 #define MPI2_IOCSTATUS_FAILURE (0x000F)
710 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
711 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
712 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
713 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
714 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
715 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
721 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
722 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
723 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
724 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
725 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
726 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
727 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
728 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
729 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
730 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
731 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
732 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
738 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
739 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
740 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
746 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
747 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
748 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
749 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
750 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
751 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
752 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
753 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
754 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
755 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
761 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
762 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
768 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
774 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
780 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
786 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
788 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
789 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
790 #define MPI2_IOCLOGINFO_TYPE_FC (0x2)
791 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
792 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
793 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
806 U16 FunctionDependent1; /*0x00 */
807 U8 ChainOffset; /*0x02 */
808 U8 Function; /*0x03 */
809 U16 FunctionDependent2; /*0x04 */
810 U8 FunctionDependent3; /*0x06 */
811 U8 MsgFlags; /*0x07 */
812 U8 VP_ID; /*0x08 */
813 U8 VF_ID; /*0x09 */
814 U16 Reserved1; /*0x0A */
823 U16 FunctionDependent1; /*0x00 */
824 U8 MsgLength; /*0x02 */
825 U8 Function; /*0x03 */
826 U16 FunctionDependent2; /*0x04 */
827 U8 FunctionDependent3; /*0x06 */
828 U8 MsgFlags; /*0x07 */
829 U8 VP_ID; /*0x08 */
830 U8 VF_ID; /*0x09 */
831 U16 Reserved1; /*0x0A */
832 U16 FunctionDependent5; /*0x0C */
833 U16 IOCStatus; /*0x0E */
834 U32 IOCLogInfo; /*0x10 */
841 U8 Dev; /*0x00 */
842 U8 Unit; /*0x01 */
843 U8 Minor; /*0x02 */
844 U8 Major; /*0x03 */
853 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
854 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
855 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
856 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
857 #define MPI2_LUN_LEVEL_1_WORD (0xFF00)
858 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
894 * MPI Chain Element structures - for MPI v2.0 products only
927 * MPI Transaction Context Element structures - for MPI v2.0 products only
992 * MPI SGE union for IO SGL's - for MPI v2.0 products only
1004 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
1036 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
1037 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
1038 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
1039 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
1040 #define MPI2_SGE_FLAGS_DIRECTION (0x04)
1041 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
1042 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
1046 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
1047 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
1051 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
1052 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
1053 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
1054 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
1058 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
1062 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
1063 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
1070 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
1071 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
1075 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
1076 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
1077 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
1078 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
1080 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
1121 /*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
1149 /*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1152 /*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1179 /*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1204 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1205 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1209 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1213 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1214 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1218 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1219 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1220 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1221 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1225 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1226 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1227 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1228 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1229 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1230 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1233 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02)
1288 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1289 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1290 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1291 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1292 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1293 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1295 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1296 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1297 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1298 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)