Lines Matching +full:double +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0-only
3 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
5 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
11 * Apr. 21 2002 - BenH Rework bus reset code for new error handler
15 * Sep. 27 2003 - BenH Move to new driver model, fix some write posting
18 * - handle aborts correctly
19 * - retry arbitration if lost (unless higher levels do this for us)
20 * - power down the chip when no device is detected
85 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->device->id))
96 u8 phase; member
153 enum mesh_phase phase; /* what we're currently trying to do */ member
215 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in dlog()
218 tlp = &tp->log[tp->log_ix]; in dlog()
219 slp = &ms->log[ms->log_ix]; in dlog()
220 tlp->fmt = fmt; in dlog()
221 tlp->tb = readtb(); in dlog()
222 tlp->phase = (ms->msgphase << 4) + ms->phase; in dlog()
223 tlp->bs0 = ms->mesh->bus_status0; in dlog()
224 tlp->bs1 = ms->mesh->bus_status1; in dlog()
225 tlp->tgt = ms->conn_tgt; in dlog()
226 tlp->d = a; in dlog()
228 if (++tp->log_ix >= N_DBG_LOG) in dlog()
229 tp->log_ix = 0; in dlog()
230 if (tp->n_log < N_DBG_LOG) in dlog()
231 ++tp->n_log; in dlog()
232 if (++ms->log_ix >= N_DBG_SLOG) in dlog()
233 ms->log_ix = 0; in dlog()
234 if (ms->n_log < N_DBG_SLOG) in dlog()
235 ++ms->n_log; in dlog()
240 struct mesh_target *tp = &ms->tgts[t]; in dumplog()
244 if (tp->n_log == 0) in dumplog()
246 i = tp->log_ix - tp->n_log; in dumplog()
249 tp->n_log = 0; in dumplog()
251 lp = &tp->log[i]; in dumplog()
253 t, lp->bs1, lp->bs0, lp->phase); in dumplog()
255 printk("tb=%10u ", lp->tb); in dumplog()
257 printk(lp->fmt, lp->d); in dumplog()
261 } while (i != tp->log_ix); in dumplog()
269 if (ms->n_log == 0) in dumpslog()
271 i = ms->log_ix - ms->n_log; in dumpslog()
274 ms->n_log = 0; in dumpslog()
276 lp = &ms->log[i]; in dumpslog()
278 lp->bs1, lp->bs0, lp->phase, lp->tgt); in dumpslog()
280 printk("tb=%10u ", lp->tb); in dumpslog()
282 printk(lp->fmt, lp->d); in dumpslog()
286 } while (i != ms->log_ix); in dumpslog()
305 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_dump_regs()
306 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_dump_regs()
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence, in mesh_dump_regs()
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count, in mesh_dump_regs()
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt, in mesh_dump_regs()
317 mr->sync_params); in mesh_dump_regs()
318 while(in_8(&mr->fifo_count)) in mesh_dump_regs()
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo)); in mesh_dump_regs()
321 in_le32(&md->status), in_le32(&md->cmdptr)); in mesh_dump_regs()
322 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n", in mesh_dump_regs()
323 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); in mesh_dump_regs()
325 ms->dma_started, ms->dma_count, ms->n_msgout); in mesh_dump_regs()
327 tp = &ms->tgts[t]; in mesh_dump_regs()
328 if (tp->current_req == NULL) in mesh_dump_regs()
331 t, tp->current_req, tp->data_goes_out, tp->saved_ptr); in mesh_dump_regs()
341 (void)in_8(&mr->mesh_id); in mesh_flush_io()
351 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_init()
352 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_init()
358 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_init()
359 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_init()
360 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_init()
361 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_init()
364 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_init()
365 out_8(&mr->source_id, ms->host->this_id); in mesh_init()
366 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_init()
367 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
373 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_init()
376 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_init()
384 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */ in mesh_init()
385 out_8(&mr->sequence, SEQ_FLUSHFIFO); in mesh_init()
388 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_init()
389 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_init()
391 ms->phase = idle; in mesh_init()
392 ms->msgphase = msg_none; in mesh_init()
398 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_start_cmd()
401 id = cmd->device->id; in mesh_start_cmd()
402 ms->current_req = cmd; in mesh_start_cmd()
403 ms->tgts[id].data_goes_out = cmd->sc_data_direction == DMA_TO_DEVICE; in mesh_start_cmd()
404 ms->tgts[id].current_req = cmd; in mesh_start_cmd()
410 for (i = 0; i < cmd->cmd_len; ++i) in mesh_start_cmd()
411 printk(" %x", cmd->cmnd[i]); in mesh_start_cmd()
416 if (ms->dma_started) in mesh_start_cmd()
417 panic("mesh: double DMA start !\n"); in mesh_start_cmd()
419 ms->phase = arbitrating; in mesh_start_cmd()
420 ms->msgphase = msg_none; in mesh_start_cmd()
421 ms->data_ptr = 0; in mesh_start_cmd()
422 ms->dma_started = 0; in mesh_start_cmd()
423 ms->n_msgout = 0; in mesh_start_cmd()
424 ms->last_n_msgout = 0; in mesh_start_cmd()
425 ms->expect_reply = 0; in mesh_start_cmd()
426 ms->conn_tgt = id; in mesh_start_cmd()
427 ms->tgts[id].saved_ptr = 0; in mesh_start_cmd()
428 ms->stat = DID_OK; in mesh_start_cmd()
429 ms->aborting = 0; in mesh_start_cmd()
431 ms->tgts[id].n_log = 0; in mesh_start_cmd()
437 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
438 out_8(&mr->interrupt, INT_CMDDONE); in mesh_start_cmd()
439 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
443 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
445 * Some other device has the bus or is arbitrating for it - in mesh_start_cmd()
449 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
450 mr->error, mr->fifo_count)); in mesh_start_cmd()
451 for (t = 100; t > 0; --t) { in mesh_start_cmd()
452 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0) in mesh_start_cmd()
454 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
456 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
457 mr->error, mr->fifo_count)); in mesh_start_cmd()
459 if (ms->phase != arbitrating) in mesh_start_cmd()
464 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) { in mesh_start_cmd()
466 ms->stat = DID_BUS_BUSY; in mesh_start_cmd()
467 ms->phase = idle; in mesh_start_cmd()
477 out_8(&mr->dest_id, mr->source_id); in mesh_start_cmd()
491 out_8(&mr->sequence, SEQ_DISRESEL); in mesh_start_cmd()
492 if (in_8(&mr->interrupt) != 0) { in mesh_start_cmd()
494 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
495 mr->error, mr->fifo_count)); in mesh_start_cmd()
497 if (ms->phase != arbitrating) in mesh_start_cmd()
500 MKWORD(mr->interrupt, mr->exception, in mesh_start_cmd()
501 mr->error, mr->fifo_count)); in mesh_start_cmd()
504 out_8(&mr->sequence, SEQ_ARBITRATE); in mesh_start_cmd()
506 for (t = 230; t > 0; --t) { in mesh_start_cmd()
507 if (in_8(&mr->interrupt) != 0) in mesh_start_cmd()
512 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
513 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
514 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
515 /* looks like a reselection - try resetting the mesh */ in mesh_start_cmd()
517 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
518 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_start_cmd()
521 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
522 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_start_cmd()
523 out_8(&mr->sequence, SEQ_ENBRESEL); in mesh_start_cmd()
525 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t) in mesh_start_cmd()
528 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count)); in mesh_start_cmd()
530 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL) in mesh_start_cmd()
531 && (in_8(&mr->bus_status0) & BS0_IO)) { in mesh_start_cmd()
553 if (ms->phase != idle || ms->current_req != NULL) { in mesh_start()
554 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)", in mesh_start()
555 ms->phase, ms); in mesh_start()
559 while (ms->phase == idle) { in mesh_start()
561 for (cmd = ms->request_q; ; cmd = (struct scsi_cmnd *) cmd->host_scribble) { in mesh_start()
564 if (ms->tgts[cmd->device->id].current_req == NULL) in mesh_start()
568 next = (struct scsi_cmnd *) cmd->host_scribble; in mesh_start()
570 ms->request_q = next; in mesh_start()
572 prev->host_scribble = (void *) next; in mesh_start()
574 ms->request_qtail = prev; in mesh_start()
583 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in mesh_done()
585 cmd = ms->current_req; in mesh_done()
586 ms->current_req = NULL; in mesh_done()
587 tp->current_req = NULL; in mesh_done()
591 set_host_byte(cmd, ms->stat); in mesh_done()
592 set_status_byte(cmd, mcmd->status); in mesh_done()
593 if (ms->stat == DID_OK) in mesh_done()
594 scsi_msg_to_host_byte(cmd, mcmd->message); in mesh_done()
597 cmd->result, ms->data_ptr, scsi_bufflen(cmd)); in mesh_done()
600 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3) in mesh_done()
601 && cmd->request_buffer != 0) { in mesh_done()
602 unsigned char *b = cmd->request_buffer; in mesh_done()
608 mcmd->this_residual -= ms->data_ptr; in mesh_done()
612 out_8(&ms->mesh->sequence, SEQ_ENBRESEL); in mesh_done()
613 mesh_flush_io(ms->mesh); in mesh_done()
615 ms->phase = idle; in mesh_done()
622 int i = ms->n_msgout; in add_sdtr_msg()
624 ms->msgout[i] = EXTENDED_MESSAGE; in add_sdtr_msg()
625 ms->msgout[i+1] = 3; in add_sdtr_msg()
626 ms->msgout[i+2] = EXTENDED_SDTR; in add_sdtr_msg()
627 ms->msgout[i+3] = mesh_sync_period/4; in add_sdtr_msg()
628 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0); in add_sdtr_msg()
629 ms->n_msgout = i + 5; in add_sdtr_msg()
634 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in set_sdtr()
635 volatile struct mesh_regs __iomem *mr = ms->mesh; in set_sdtr()
638 tp->sdtr_state = sdtr_done; in set_sdtr()
641 if (SYNC_OFF(tp->sync_params)) in set_sdtr()
643 ms->conn_tgt); in set_sdtr()
644 tp->sync_params = ASYNC_PARAMS; in set_sdtr()
645 out_8(&mr->sync_params, ASYNC_PARAMS); in set_sdtr()
649 * We need to compute ceil(clk_freq * period / 500e6) - 2 in set_sdtr()
652 v = (ms->clk_freq / 5000) * period; in set_sdtr()
657 tr = (ms->clk_freq + 250000) / 500000; in set_sdtr()
660 v = (v + 99999) / 100000 - 2; in set_sdtr()
663 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000; in set_sdtr()
667 tp->sync_params = SYNC_PARAMS(offset, v); in set_sdtr()
668 out_8(&mr->sync_params, tp->sync_params); in set_sdtr()
670 ms->conn_tgt, tr/10, tr%10); in set_sdtr()
676 volatile struct mesh_regs __iomem *mr = ms->mesh; in start_phase()
677 volatile struct dbdma_regs __iomem *md = ms->dma; in start_phase()
678 struct scsi_cmnd *cmd = ms->current_req; in start_phase()
679 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in start_phase()
682 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence)); in start_phase()
683 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in start_phase()
684 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in start_phase()
685 switch (ms->msgphase) { in start_phase()
690 out_8(&mr->count_hi, 0); in start_phase()
691 out_8(&mr->count_lo, 1); in start_phase()
692 out_8(&mr->sequence, SEQ_MSGIN + seq); in start_phase()
693 ms->n_msgin = 0; in start_phase()
702 if (ms->n_msgout <= 0) { in start_phase()
704 ms->n_msgout); in start_phase()
706 ms->msgphase = msg_none; in start_phase()
709 if (ALLOW_DEBUG(ms->conn_tgt)) { in start_phase()
711 ms->n_msgout); in start_phase()
712 for (i = 0; i < ms->n_msgout; ++i) in start_phase()
713 printk(" %x", ms->msgout[i]); in start_phase()
716 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0], in start_phase()
717 ms->msgout[1], ms->msgout[2])); in start_phase()
718 out_8(&mr->count_hi, 0); in start_phase()
719 out_8(&mr->sequence, SEQ_FLUSHFIFO); in start_phase()
726 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) { in start_phase()
727 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0); in start_phase()
728 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */ in start_phase()
731 out_8(&mr->count_lo, 1); in start_phase()
732 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
733 out_8(&mr->bus_status0, 0); /* release explicit ATN */ in start_phase()
734 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0); in start_phase()
736 if (ms->n_msgout == 1) { in start_phase()
745 out_8(&mr->count_lo, ms->n_msgout - 1); in start_phase()
746 out_8(&mr->sequence, SEQ_MSGOUT + seq); in start_phase()
747 for (i = 0; i < ms->n_msgout - 1; ++i) in start_phase()
748 out_8(&mr->fifo, ms->msgout[i]); in start_phase()
754 ms->msgphase); in start_phase()
757 switch (ms->phase) { in start_phase()
759 out_8(&mr->dest_id, ms->conn_tgt); in start_phase()
760 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN); in start_phase()
763 out_8(&mr->sync_params, tp->sync_params); in start_phase()
764 out_8(&mr->count_hi, 0); in start_phase()
766 out_8(&mr->count_lo, cmd->cmd_len); in start_phase()
767 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
768 for (i = 0; i < cmd->cmd_len; ++i) in start_phase()
769 out_8(&mr->fifo, cmd->cmnd[i]); in start_phase()
771 out_8(&mr->count_lo, 6); in start_phase()
772 out_8(&mr->sequence, SEQ_COMMAND + seq); in start_phase()
774 out_8(&mr->fifo, 0); in start_phase()
779 if (!ms->dma_started) { in start_phase()
781 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds)); in start_phase()
782 out_le32(&md->control, (RUN << 16) | RUN); in start_phase()
783 ms->dma_started = 1; in start_phase()
785 nb = ms->dma_count; in start_phase()
788 ms->dma_count -= nb; in start_phase()
789 ms->data_ptr += nb; in start_phase()
790 out_8(&mr->count_lo, nb); in start_phase()
791 out_8(&mr->count_hi, nb >> 8); in start_phase()
792 out_8(&mr->sequence, (tp->data_goes_out? in start_phase()
796 out_8(&mr->count_hi, 0); in start_phase()
797 out_8(&mr->count_lo, 1); in start_phase()
798 out_8(&mr->sequence, SEQ_STATUS + seq); in start_phase()
802 out_8(&mr->sequence, SEQ_ENBRESEL); in start_phase()
806 MKWORD(mr->interrupt, mr->exception, mr->error, in start_phase()
807 mr->fifo_count)); in start_phase()
808 out_8(&mr->sequence, SEQ_BUSFREE); in start_phase()
811 printk(KERN_ERR "mesh: start_phase called with phase=%d\n", in start_phase()
812 ms->phase); in start_phase()
820 volatile struct mesh_regs __iomem *mr = ms->mesh; in get_msgin()
823 n = mr->fifo_count; in get_msgin()
825 i = ms->n_msgin; in get_msgin()
826 ms->n_msgin = i + n; in get_msgin()
827 for (; n > 0; --n) in get_msgin()
828 ms->msgin[i++] = in_8(&mr->fifo); in get_msgin()
837 if (ms->n_msgin > 0) { in msgin_length()
838 b = ms->msgin[0]; in msgin_length()
841 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2; in msgin_length()
843 /* 2-byte message */ in msgin_length()
852 volatile struct mesh_regs __iomem *mr = ms->mesh; in reselected()
857 switch (ms->phase) { in reselected()
861 if ((cmd = ms->current_req) != NULL) { in reselected()
863 cmd->host_scribble = (void *) ms->request_q; in reselected()
864 if (ms->request_q == NULL) in reselected()
865 ms->request_qtail = cmd; in reselected()
866 ms->request_q = cmd; in reselected()
867 tp = &ms->tgts[cmd->device->id]; in reselected()
868 tp->current_req = NULL; in reselected()
872 ms->phase = reselecting; in reselected()
878 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n", in reselected()
879 ms->msgphase, ms->phase, ms->conn_tgt); in reselected()
880 dumplog(ms, ms->conn_tgt); in reselected()
884 if (ms->dma_started) { in reselected()
888 ms->current_req = NULL; in reselected()
889 ms->phase = dataing; in reselected()
890 ms->msgphase = msg_in; in reselected()
891 ms->n_msgout = 0; in reselected()
892 ms->last_n_msgout = 0; in reselected()
893 prev = ms->conn_tgt; in reselected()
898 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) { in reselected()
901 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
904 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
908 MKWORD(0, mr->error, mr->exception, mr->fifo_count)); in reselected()
910 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in reselected()
913 out_8(&mr->sequence, SEQ_ENBRESEL); in reselected()
916 out_8(&mr->sync_params, ASYNC_PARAMS); in reselected()
921 if (in_8(&mr->fifo_count) == 0) { in reselected()
923 ms->conn_tgt = ms->host->this_id; in reselected()
928 b = in_8(&mr->fifo); in reselected()
930 } while (in_8(&mr->fifo_count)); in reselected()
932 if ((b & (1 << t)) != 0 && t != ms->host->this_id) in reselected()
934 if (b != (1 << t) + (1 << ms->host->this_id)) { in reselected()
936 ms->conn_tgt = ms->host->this_id; in reselected()
944 ms->conn_tgt = t; in reselected()
945 tp = &ms->tgts[t]; in reselected()
946 out_8(&mr->sync_params, tp->sync_params); in reselected()
950 tp->saved_ptr, tp->data_goes_out, tp->current_req); in reselected()
952 ms->current_req = tp->current_req; in reselected()
953 if (tp->current_req == NULL) { in reselected()
957 ms->data_ptr = tp->saved_ptr; in reselected()
959 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception)); in reselected()
964 dumplog(ms, ms->conn_tgt); in reselected()
966 ms->data_ptr = 0; in reselected()
967 ms->aborting = 1; in reselected()
973 ms->msgout[0] = ABORT; in do_abort()
974 ms->n_msgout = 1; in do_abort()
975 ms->aborting = 1; in do_abort()
976 ms->stat = DID_ABORT; in do_abort()
985 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_reset()
988 tp = &ms->tgts[tgt]; in handle_reset()
989 if ((cmd = tp->current_req) != NULL) { in handle_reset()
991 tp->current_req = NULL; in handle_reset()
994 ms->tgts[tgt].sdtr_state = do_sdtr; in handle_reset()
995 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in handle_reset()
997 ms->current_req = NULL; in handle_reset()
998 while ((cmd = ms->request_q) != NULL) { in handle_reset()
999 ms->request_q = (struct scsi_cmnd *) cmd->host_scribble; in handle_reset()
1003 ms->phase = idle; in handle_reset()
1004 ms->msgphase = msg_none; in handle_reset()
1005 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_reset()
1006 out_8(&mr->sequence, SEQ_FLUSHFIFO); in handle_reset()
1009 out_8(&mr->sync_params, ASYNC_PARAMS); in handle_reset()
1010 out_8(&mr->sequence, SEQ_ENBRESEL); in handle_reset()
1017 struct Scsi_Host *dev = ms->host; in do_mesh_interrupt()
1019 spin_lock_irqsave(dev->host_lock, flags); in do_mesh_interrupt()
1021 spin_unlock_irqrestore(dev->host_lock, flags); in do_mesh_interrupt()
1028 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_error()
1030 err = in_8(&mr->error); in handle_error()
1031 exc = in_8(&mr->exception); in handle_error()
1032 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in handle_error()
1034 MKWORD(err, exc, mr->fifo_count, mr->count_lo)); in handle_error()
1039 while ((in_8(&mr->bus_status1) & BS1_RST) != 0) in handle_error()
1042 if (ms->dma_started) in handle_error()
1054 if (!ms->aborting) { in handle_error()
1056 ms->conn_tgt); in handle_error()
1057 dumplog(ms, ms->conn_tgt); in handle_error()
1060 out_8(&mr->interrupt, INT_CMDDONE); in handle_error()
1061 ms->stat = DID_ABORT; in handle_error()
1066 if (ms->msgphase == msg_in) { in handle_error()
1068 ms->conn_tgt); in handle_error()
1069 ms->msgout[0] = MSG_PARITY_ERROR; in handle_error()
1070 ms->n_msgout = 1; in handle_error()
1071 ms->msgphase = msg_in_bad; in handle_error()
1075 if (ms->stat == DID_OK) { in handle_error()
1077 ms->conn_tgt); in handle_error()
1078 ms->stat = DID_PARITY; in handle_error()
1080 count = (mr->count_hi << 8) + mr->count_lo; in handle_error()
1085 out_8(&mr->sequence, mr->sequence); in handle_error()
1110 dumplog(ms, ms->conn_tgt); in handle_error()
1111 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) { in handle_error()
1117 ms->stat = DID_ERROR; in handle_error()
1124 volatile struct mesh_regs __iomem *mr = ms->mesh; in handle_exception()
1126 exc = in_8(&mr->exception); in handle_exception()
1127 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE); in handle_exception()
1134 ms->stat = DID_BUS_BUSY; in handle_exception()
1138 ms->stat = DID_BAD_TARGET; in handle_exception()
1147 dumplog(ms, ms->conn_tgt); in handle_exception()
1156 struct scsi_cmnd *cmd = ms->current_req; in handle_msgin()
1157 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in handle_msgin()
1159 if (ms->n_msgin == 0) in handle_msgin()
1161 code = ms->msgin[0]; in handle_msgin()
1162 if (ALLOW_DEBUG(ms->conn_tgt)) { in handle_msgin()
1163 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin); in handle_msgin()
1164 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1165 printk(" %x", ms->msgin[i]); in handle_msgin()
1169 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2])); in handle_msgin()
1171 ms->expect_reply = 0; in handle_msgin()
1172 ms->n_msgout = 0; in handle_msgin()
1173 if (ms->n_msgin < msgin_length(ms)) in handle_msgin()
1176 mesh_priv(cmd)->message = code; in handle_msgin()
1181 switch (ms->msgin[2]) { in handle_msgin()
1183 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6] in handle_msgin()
1184 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8); in handle_msgin()
1187 if (tp->sdtr_state != sdtr_sent) { in handle_msgin()
1192 if (ms->msgout[3] < ms->msgin[3]) in handle_msgin()
1193 ms->msgout[3] = ms->msgin[3]; in handle_msgin()
1194 if (ms->msgout[4] > ms->msgin[4]) in handle_msgin()
1195 ms->msgout[4] = ms->msgin[4]; in handle_msgin()
1196 set_sdtr(ms, ms->msgout[3], ms->msgout[4]); in handle_msgin()
1197 ms->msgphase = msg_out; in handle_msgin()
1199 set_sdtr(ms, ms->msgin[3], ms->msgin[4]); in handle_msgin()
1207 tp->saved_ptr = ms->data_ptr; in handle_msgin()
1210 ms->data_ptr = tp->saved_ptr; in handle_msgin()
1213 ms->phase = disconnecting; in handle_msgin()
1218 if (tp->sdtr_state == sdtr_sent) in handle_msgin()
1227 ms->msgphase = msg_out; in handle_msgin()
1228 } else if (code != cmd->device->lun + IDENTIFY_BASE) { in handle_msgin()
1231 "target %d\n", code - IDENTIFY_BASE, in handle_msgin()
1232 cmd->device->lun, ms->conn_tgt); in handle_msgin()
1242 ms->conn_tgt); in handle_msgin()
1243 for (i = 0; i < ms->n_msgin; ++i) in handle_msgin()
1244 printk(" %x", ms->msgin[i]); in handle_msgin()
1246 ms->msgout[0] = MESSAGE_REJECT; in handle_msgin()
1247 ms->n_msgout = 1; in handle_msgin()
1248 ms->msgphase = msg_out; in handle_msgin()
1260 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out? in set_dma_cmds()
1262 dcmds = ms->dma_cmds; in set_dma_cmds()
1267 mesh_priv(cmd)->this_residual = scsi_bufflen(cmd); in set_dma_cmds()
1274 off = ms->data_ptr; in set_dma_cmds()
1280 total += scl->length; in set_dma_cmds()
1282 off -= dma_len; in set_dma_cmds()
1287 dcmds->req_count = cpu_to_le16(dma_len - off); in set_dma_cmds()
1288 dcmds->command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1289 dcmds->phy_addr = cpu_to_le32(dma_addr + off); in set_dma_cmds()
1290 dcmds->xfer_status = 0; in set_dma_cmds()
1292 dtot += dma_len - off; in set_dma_cmds()
1303 dcmds->req_count = cpu_to_le16(dtot); in set_dma_cmds()
1304 dcmds->phy_addr = cpu_to_le32(virt_to_phys(mesh_extra_buf)); in set_dma_cmds()
1305 dcmds->xfer_status = 0; in set_dma_cmds()
1308 dma_cmd += OUTPUT_LAST - OUTPUT_MORE; in set_dma_cmds()
1309 dcmds[-1].command = cpu_to_le16(dma_cmd); in set_dma_cmds()
1311 dcmds->command = cpu_to_le16(DBDMA_STOP); in set_dma_cmds()
1312 ms->dma_count = dtot; in set_dma_cmds()
1317 volatile struct dbdma_regs __iomem *md = ms->dma; in halt_dma()
1318 volatile struct mesh_regs __iomem *mr = ms->mesh; in halt_dma()
1319 struct scsi_cmnd *cmd = ms->current_req; in halt_dma()
1322 if (!ms->tgts[ms->conn_tgt].data_goes_out) { in halt_dma()
1325 while (t > 0 && in_8(&mr->fifo_count) != 0 in halt_dma()
1326 && (in_le32(&md->status) & ACTIVE) != 0) { in halt_dma()
1327 --t; in halt_dma()
1331 out_le32(&md->control, RUN << 16); /* turn off RUN bit */ in halt_dma()
1332 nb = (mr->count_hi << 8) + mr->count_lo; in halt_dma()
1334 MKWORD(0, mr->fifo_count, 0, nb)); in halt_dma()
1335 if (ms->tgts[ms->conn_tgt].data_goes_out) in halt_dma()
1336 nb += mr->fifo_count; in halt_dma()
1339 ms->data_ptr -= nb; in halt_dma()
1340 dlog(ms, "data_ptr %x", ms->data_ptr); in halt_dma()
1341 if (ms->data_ptr < 0) { in halt_dma()
1343 ms->data_ptr, nb, ms); in halt_dma()
1344 ms->data_ptr = 0; in halt_dma()
1346 dumplog(ms, ms->conn_tgt); in halt_dma()
1350 ms->data_ptr > scsi_bufflen(cmd)) { in halt_dma()
1353 ms->conn_tgt, ms->data_ptr, scsi_bufflen(cmd), in halt_dma()
1354 ms->tgts[ms->conn_tgt].data_goes_out); in halt_dma()
1358 ms->dma_started = 0; in halt_dma()
1363 volatile struct mesh_regs __iomem *mr = ms->mesh; in phase_mismatch()
1364 int phase; in phase_mismatch() local
1367 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count)); in phase_mismatch()
1368 phase = in_8(&mr->bus_status0) & BS0_PHASE; in phase_mismatch()
1369 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) { in phase_mismatch()
1371 out_8(&mr->count_lo, 1); in phase_mismatch()
1372 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in phase_mismatch()
1375 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in phase_mismatch()
1376 ms->msgphase = msg_out_last; in phase_mismatch()
1380 if (ms->msgphase == msg_in) { in phase_mismatch()
1382 if (ms->n_msgin) in phase_mismatch()
1386 if (ms->dma_started) in phase_mismatch()
1388 if (mr->fifo_count) { in phase_mismatch()
1389 out_8(&mr->sequence, SEQ_FLUSHFIFO); in phase_mismatch()
1394 ms->msgphase = msg_none; in phase_mismatch()
1395 switch (phase) { in phase_mismatch()
1397 ms->tgts[ms->conn_tgt].data_goes_out = 0; in phase_mismatch()
1398 ms->phase = dataing; in phase_mismatch()
1401 ms->tgts[ms->conn_tgt].data_goes_out = 1; in phase_mismatch()
1402 ms->phase = dataing; in phase_mismatch()
1405 ms->phase = commanding; in phase_mismatch()
1408 ms->phase = statusing; in phase_mismatch()
1411 ms->msgphase = msg_in; in phase_mismatch()
1412 ms->n_msgin = 0; in phase_mismatch()
1415 ms->msgphase = msg_out; in phase_mismatch()
1416 if (ms->n_msgout == 0) { in phase_mismatch()
1417 if (ms->aborting) { in phase_mismatch()
1420 if (ms->last_n_msgout == 0) { in phase_mismatch()
1423 ms->msgout[0] = NOP; in phase_mismatch()
1424 ms->last_n_msgout = 1; in phase_mismatch()
1426 ms->n_msgout = ms->last_n_msgout; in phase_mismatch()
1431 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase); in phase_mismatch()
1432 ms->stat = DID_ERROR; in phase_mismatch()
1442 volatile struct mesh_regs __iomem *mr = ms->mesh; in cmd_complete()
1443 struct scsi_cmnd *cmd = ms->current_req; in cmd_complete()
1444 struct mesh_target *tp = &ms->tgts[ms->conn_tgt]; in cmd_complete()
1447 dlog(ms, "cmd_complete fc=%x", mr->fifo_count); in cmd_complete()
1448 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0); in cmd_complete()
1449 switch (ms->msgphase) { in cmd_complete()
1451 /* huh? we expected a phase mismatch */ in cmd_complete()
1452 ms->n_msgin = 0; in cmd_complete()
1453 ms->msgphase = msg_in; in cmd_complete()
1460 if (ms->n_msgin < n) { in cmd_complete()
1461 out_8(&mr->count_lo, n - ms->n_msgin); in cmd_complete()
1462 out_8(&mr->sequence, SEQ_MSGIN + seq); in cmd_complete()
1464 ms->msgphase = msg_none; in cmd_complete()
1471 out_8(&mr->sequence, SEQ_FLUSHFIFO); in cmd_complete()
1474 out_8(&mr->count_lo, 1); in cmd_complete()
1475 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg); in cmd_complete()
1487 * wait for the phase mismatch interrupt, then in cmd_complete()
1490 out_8(&mr->count_lo, 1); in cmd_complete()
1491 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN); in cmd_complete()
1493 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0) in cmd_complete()
1496 MKWORD(mr->error, mr->exception, in cmd_complete()
1497 mr->fifo_count, mr->count_lo)); in cmd_complete()
1498 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) { in cmd_complete()
1500 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1501 ms->n_msgout = 0; in cmd_complete()
1502 if (in_8(&mr->interrupt) & INT_ERROR) { in cmd_complete()
1504 in_8(&mr->error)); in cmd_complete()
1508 if (in_8(&mr->exception) != EXC_PHASEMM) in cmd_complete()
1510 in_8(&mr->exception)); in cmd_complete()
1513 in_8(&mr->bus_status0)); in cmd_complete()
1517 if (in_8(&mr->bus_status0) & BS0_REQ) { in cmd_complete()
1518 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg); in cmd_complete()
1521 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]); in cmd_complete()
1522 ms->msgphase = msg_out_last; in cmd_complete()
1524 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN); in cmd_complete()
1525 ms->msgphase = msg_out_xxx; in cmd_complete()
1530 ms->last_n_msgout = ms->n_msgout; in cmd_complete()
1531 ms->n_msgout = 0; in cmd_complete()
1532 ms->msgphase = ms->expect_reply? msg_in: msg_none; in cmd_complete()
1537 switch (ms->phase) { in cmd_complete()
1539 printk(KERN_ERR "mesh: interrupt in idle phase?\n"); in cmd_complete()
1543 dlog(ms, "Selecting phase at command completion",0); in cmd_complete()
1544 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt), in cmd_complete()
1545 (cmd? cmd->device->lun: 0)); in cmd_complete()
1546 ms->n_msgout = 1; in cmd_complete()
1547 ms->expect_reply = 0; in cmd_complete()
1548 if (ms->aborting) { in cmd_complete()
1549 ms->msgout[0] = ABORT; in cmd_complete()
1550 ms->n_msgout++; in cmd_complete()
1551 } else if (tp->sdtr_state == do_sdtr) { in cmd_complete()
1554 ms->expect_reply = 1; in cmd_complete()
1555 tp->sdtr_state = sdtr_sent; in cmd_complete()
1557 ms->msgphase = msg_out; in cmd_complete()
1562 * which will give us a phase mismatch interrupt in cmd_complete()
1566 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) { in cmd_complete()
1567 if (--t < 0) { in cmd_complete()
1568 dlog(ms, "impatient for req", ms->n_msgout); in cmd_complete()
1569 ms->msgphase = msg_none; in cmd_complete()
1576 if (ms->dma_count != 0) { in cmd_complete()
1581 * We can get a phase mismatch here if the target in cmd_complete()
1582 * changes to the status phase, even though we have in cmd_complete()
1588 * error and phase mismatch exception. in cmd_complete()
1590 out_8(&mr->sequence, 0); in cmd_complete()
1591 out_8(&mr->interrupt, in cmd_complete()
1599 mcmd->status = mr->fifo; in cmd_complete()
1602 mcmd->status); in cmd_complete()
1604 ms->msgphase = msg_in; in cmd_complete()
1610 ms->current_req = NULL; in cmd_complete()
1611 ms->phase = idle; in cmd_complete()
1617 ++ms->phase; in cmd_complete()
1632 cmd->host_scribble = NULL; in mesh_queue_lck()
1634 ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_queue_lck()
1636 if (ms->request_q == NULL) in mesh_queue_lck()
1637 ms->request_q = cmd; in mesh_queue_lck()
1639 ms->request_qtail->host_scribble = (void *) cmd; in mesh_queue_lck()
1640 ms->request_qtail = cmd; in mesh_queue_lck()
1642 if (ms->phase == idle) in mesh_queue_lck()
1657 volatile struct mesh_regs __iomem *mr = ms->mesh; in DEF_SCSI_QCMD()
1661 if (ALLOW_DEBUG(ms->conn_tgt)) in DEF_SCSI_QCMD()
1663 "phase=%d msgphase=%d\n", mr->bus_status0, in DEF_SCSI_QCMD()
1664 mr->interrupt, mr->exception, mr->error, in DEF_SCSI_QCMD()
1665 ms->phase, ms->msgphase); in DEF_SCSI_QCMD()
1667 while ((intr = in_8(&mr->interrupt)) != 0) { in DEF_SCSI_QCMD()
1669 MKWORD(intr, mr->error, mr->exception, mr->sequence)); in DEF_SCSI_QCMD()
1675 out_8(&mr->interrupt, INT_CMDDONE); in DEF_SCSI_QCMD()
1687 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_abort()
1691 dumplog(ms, cmd->device->id); in mesh_abort()
1704 struct mesh_state *ms = (struct mesh_state *) cmd->device->host->hostdata; in mesh_host_reset()
1705 volatile struct mesh_regs __iomem *mr = ms->mesh; in mesh_host_reset()
1706 volatile struct dbdma_regs __iomem *md = ms->dma; in mesh_host_reset()
1711 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_host_reset()
1713 if (ms->dma_started) in mesh_host_reset()
1717 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */ in mesh_host_reset()
1718 out_8(&mr->exception, 0xff); /* clear all exception bits */ in mesh_host_reset()
1719 out_8(&mr->error, 0xff); /* clear all error bits */ in mesh_host_reset()
1720 out_8(&mr->sequence, SEQ_RESETMESH); in mesh_host_reset()
1723 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_host_reset()
1724 out_8(&mr->source_id, ms->host->this_id); in mesh_host_reset()
1725 out_8(&mr->sel_timeout, 25); /* 250ms */ in mesh_host_reset()
1726 out_8(&mr->sync_params, ASYNC_PARAMS); in mesh_host_reset()
1729 out_8(&mr->bus_status1, BS1_RST); /* assert RST */ in mesh_host_reset()
1732 out_8(&mr->bus_status1, 0); /* negate RST */ in mesh_host_reset()
1737 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_host_reset()
1746 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 1); in set_mesh_power()
1749 pmac_call_feature(PMAC_FTR_MESH_ENABLE, macio_get_of_node(ms->mdev), 0, 0); in set_mesh_power()
1769 if (ms->phase == sleeping) in mesh_suspend()
1772 scsi_block_requests(ms->host); in mesh_suspend()
1773 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1774 while(ms->phase != idle) { in mesh_suspend()
1775 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1777 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_suspend()
1779 ms->phase = sleeping; in mesh_suspend()
1780 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_suspend()
1781 disable_irq(ms->meshintr); in mesh_suspend()
1792 if (ms->phase != sleeping) in mesh_resume()
1797 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_resume()
1799 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_resume()
1800 enable_irq(ms->meshintr); in mesh_resume()
1801 scsi_unblock_requests(ms->host); in mesh_resume()
1820 spin_lock_irqsave(ms->host->host_lock, flags); in mesh_shutdown()
1821 mr = ms->mesh; in mesh_shutdown()
1822 out_8(&mr->intr_mask, 0); in mesh_shutdown()
1823 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE); in mesh_shutdown()
1824 out_8(&mr->bus_status1, BS1_RST); in mesh_shutdown()
1827 out_8(&mr->bus_status1, 0); in mesh_shutdown()
1828 spin_unlock_irqrestore(ms->host->host_lock, flags); in mesh_shutdown()
1858 switch (mdev->bus->chip->type) { in mesh_probe()
1872 return -ENODEV; in mesh_probe()
1877 return -EBUSY; in mesh_probe()
1885 mesh_host->base = macio_resource_start(mdev, 0); in mesh_probe()
1886 mesh_host->irq = macio_irq(mdev, 0); in mesh_probe()
1887 ms = (struct mesh_state *) mesh_host->hostdata; in mesh_probe()
1889 ms->host = mesh_host; in mesh_probe()
1890 ms->mdev = mdev; in mesh_probe()
1891 ms->pdev = pdev; in mesh_probe()
1893 ms->mesh = ioremap(macio_resource_start(mdev, 0), 0x1000); in mesh_probe()
1894 if (ms->mesh == NULL) { in mesh_probe()
1898 ms->dma = ioremap(macio_resource_start(mdev, 1), 0x1000); in mesh_probe()
1899 if (ms->dma == NULL) { in mesh_probe()
1901 iounmap(ms->mesh); in mesh_probe()
1905 ms->meshintr = macio_irq(mdev, 0); in mesh_probe()
1906 ms->dmaintr = macio_irq(mdev, 1); in mesh_probe()
1911 ms->dma_cmd_size = (mesh_host->sg_tablesize + 2) * sizeof(struct dbdma_cmd); in mesh_probe()
1914 * enough or until we get some macio-specific versions in mesh_probe()
1916 dma_cmd_space = dma_alloc_coherent(&macio_get_pci_dev(mdev)->dev, in mesh_probe()
1917 ms->dma_cmd_size, &dma_cmd_bus, in mesh_probe()
1924 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space); in mesh_probe()
1925 ms->dma_cmd_space = dma_cmd_space; in mesh_probe()
1926 ms->dma_cmd_bus = dma_cmd_bus + ((unsigned long)ms->dma_cmds) in mesh_probe()
1927 - (unsigned long)dma_cmd_space; in mesh_probe()
1928 ms->current_req = NULL; in mesh_probe()
1930 ms->tgts[tgt].sdtr_state = do_sdtr; in mesh_probe()
1931 ms->tgts[tgt].sync_params = ASYNC_PARAMS; in mesh_probe()
1932 ms->tgts[tgt].current_req = NULL; in mesh_probe()
1935 if ((cfp = of_get_property(mesh, "clock-frequency", NULL))) in mesh_probe()
1936 ms->clk_freq = *cfp; in mesh_probe()
1939 ms->clk_freq = 50000000; in mesh_probe()
1945 minper = 1000000000 / (ms->clk_freq / 5); /* ns */ in mesh_probe()
1956 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) { in mesh_probe()
1957 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr); in mesh_probe()
1962 if (scsi_add_host(mesh_host, &mdev->ofdev.dev)) in mesh_probe()
1969 free_irq(ms->meshintr, ms); in mesh_probe()
1976 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_probe()
1977 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_probe()
1979 iounmap(ms->dma); in mesh_probe()
1980 iounmap(ms->mesh); in mesh_probe()
1986 return -ENODEV; in mesh_probe()
1992 struct Scsi_Host *mesh_host = ms->host; in mesh_remove()
1996 free_irq(ms->meshintr, ms); in mesh_remove()
2005 iounmap(ms->mesh); in mesh_remove()
2006 iounmap(ms->dma); in mesh_remove()
2009 dma_free_coherent(&macio_get_pci_dev(mdev)->dev, ms->dma_cmd_size, in mesh_remove()
2010 ms->dma_cmd_space, ms->dma_cmd_bus); in mesh_remove()