3  *    Copyright (c) 2019-2020 Microchip Technology Inc. and its subsidiaries
5  *    Copyright 2014-2015 PMC-Sierra, Inc.
6  *    Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
56 	struct sas_phy *phy;  member
74 	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
75 	unsigned char model[16];        /* bytes 16-31 of inquiry data */
113 	int external;   /* 1-from external array 0-not <0-unknown */
216 	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
256 	/* Address of h->q[x] is passed to intr handler to know which queue */
258 	char intrname[MAX_REPLY_QUEUES][16];	/* "hpsa0-msix00" names */
423 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command()
424 	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);  in SA5_submit_command()
430 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_no_read()
436 	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);  in SA5_submit_command_ioaccel2()
447 		h->interrupts_enabled = 1;  in SA5_intr_mask()
448 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
449 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
451 		h->interrupts_enabled = 0;  in SA5_intr_mask()
453 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
454 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
464 		h->interrupts_enabled = 1;  in SA5B_intr_mask()
465 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
466 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
468 		h->interrupts_enabled = 0;  in SA5B_intr_mask()
470 		       h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
471 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
478 		h->interrupts_enabled = 1;  in SA5_performant_intr_mask()
479 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
480 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
482 		h->interrupts_enabled = 0;  in SA5_performant_intr_mask()
484 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
485 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
491 	struct reply_queue_buffer *rq = &h->reply_queue[q];  in SA5_performant_completed()
495 	if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) {  in SA5_performant_completed()
499 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
500 		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);  in SA5_performant_completed()
504 		(void) readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_completed()
507 	if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {  in SA5_performant_completed()
508 		register_value = rq->head[rq->current_entry];  in SA5_performant_completed()
509 		rq->current_entry++;  in SA5_performant_completed()
510 		atomic_dec(&h->commands_outstanding);  in SA5_performant_completed()
515 	if (rq->current_entry == h->max_commands) {  in SA5_performant_completed()
516 		rq->current_entry = 0;  in SA5_performant_completed()
517 		rq->wraparound ^= 1;  in SA5_performant_completed()
530 		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);  in SA5_completed()
533 		atomic_dec(&h->commands_outstanding);  in SA5_completed()
537 		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",  in SA5_completed()
540 		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");  in SA5_completed()
551 		readl(h->vaddr + SA5_INTR_STATUS);  in SA5_intr_pending()
557 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_performant_intr_pending()
563 	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);  in SA5_performant_intr_pending()
571 	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);  in SA5_ioaccel_mode1_intr_pending()
582 	return readl(h->vaddr + SA5_INTR_STATUS) & SA5B_INTR_PENDING;  in SA5B_intr_pending()
593 	struct reply_queue_buffer *rq = &h->reply_queue[q];  in SA5_ioaccel_mode1_completed()
595 	BUG_ON(q >= h->nreply_queues);  in SA5_ioaccel_mode1_completed()
597 	register_value = rq->head[rq->current_entry];  in SA5_ioaccel_mode1_completed()
599 		rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;  in SA5_ioaccel_mode1_completed()
600 		if (++rq->current_entry == rq->size)  in SA5_ioaccel_mode1_completed()
601 			rq->current_entry = 0;  in SA5_ioaccel_mode1_completed()
609 		writel((q << 24) | rq->current_entry, h->vaddr +  in SA5_ioaccel_mode1_completed()
611 		atomic_dec(&h->commands_outstanding);  in SA5_ioaccel_mode1_completed()