Lines Matching +full:per +full:- +full:port

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
24 * except for SCSI CDB which remains big endian per SCSI standards.
49 * 0x1 -> port#0 can be selected,
50 * 0x2 -> port#1 can be selected.
65 #define SISL_MSI_ASYNC_ERROR 3 /* master only - for AFU async error */
112 * a FC port. If the port went down on an active IO, it will set
132 * If the link is down or logged out before AFU selects the port, either
133 * it will choose the other port or we will get afu_rc=0x20 (no_channel)
134 * if there is no valid port to use.
138 * NOLOGI or LINKDOWN can be retried if the other port is up.
147 #define SISL_FC_RC_NOLOGI 0x54 /* port not logged in, in-flight cmds */
150 #define SISL_FC_RC_LINKDOWN 0x57 /* link down, in-flight cmds */
180 u8 port; member
222 /* MMIO space is required to support only 64-bit access */
225 * This AFU has two mechanisms to deal with endian-ness.
227 * below that specifies the endian-ness of the host.
228 * The other is a per context (i.e. application) specification
231 * endian-ness is set to be the same as the host.
233 * As per the SISlite spec, the MMIO registers are always
245 /* per context host transport MMIO */
247 __be64 endian_ctrl; /* Per context Endian Control. The AFU will
299 /* per context provisioning & control MMIO */
326 * In cxlflash, FC port/link are arranged in port pairs, each
429 #define CXLFLASH_NUM_FC_PORTS_PER_BANK 2 /* fixed # of ports per bank */
433 #define CXLFLASH_MAX_CONTEXT 512 /* number of contexts per AFU */
434 #define CXLFLASH_NUM_VLUNS 512 /* number of vluns per AFU/port */
435 #define CXLFLASH_NUM_REGS 512 /* number of registers per port */
450 struct fc_port_bank bank[CXLFLASH_MAX_FC_BANKS]; /* pages 2 - 9 */
452 /* pages 10 - 15 are reserved */
459 * +-------------------------------+
461 * | (per context) |
463 * +-------------------------------+
464 * | 512 * 128 B per context |
467 * +-------------------------------+
470 * +-------------------------------+
490 * LXT - LBA Translation Table
503 * RHT - Resource Handle Table
504 * Per the SISlite spec, RHT entries are to be 16-byte aligned
549 #define PORT_MASK(_n) ((1 << (_n)) - 1)