Lines Matching full:rb
185 void __iomem *rb; in bfa_ioc_ct_reg_init() local
188 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
190 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
191 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
192 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
195 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
196 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
197 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
198 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
199 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
200 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
201 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
203 ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG); in bfa_ioc_ct_reg_init()
204 ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG); in bfa_ioc_ct_reg_init()
205 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
206 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
207 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
208 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
209 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
215 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); in bfa_ioc_ct_reg_init()
216 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); in bfa_ioc_ct_reg_init()
217 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_reg_init()
218 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_reg_init()
223 ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG); in bfa_ioc_ct_reg_init()
224 ioc->ioc_regs.ioc_usage_sem_reg = (rb + HOST_SEM1_REG); in bfa_ioc_ct_reg_init()
225 ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG); in bfa_ioc_ct_reg_init()
226 ioc->ioc_regs.ioc_usage_reg = (rb + BFA_FW_USE_COUNT); in bfa_ioc_ct_reg_init()
227 ioc->ioc_regs.ioc_fail_sync = (rb + BFA_IOC_FAIL_SYNC); in bfa_ioc_ct_reg_init()
232 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); in bfa_ioc_ct_reg_init()
238 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
244 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
247 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
249 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
250 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
251 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
252 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
253 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
254 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
257 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
258 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
259 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
260 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
261 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
263 ioc->ioc_regs.heartbeat = (rb + CT2_BFA_IOC1_HBEAT_REG); in bfa_ioc_ct2_reg_init()
264 ioc->ioc_regs.ioc_fwstate = (rb + CT2_BFA_IOC1_STATE_REG); in bfa_ioc_ct2_reg_init()
265 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
266 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
267 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
273 ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG); in bfa_ioc_ct2_reg_init()
274 ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG); in bfa_ioc_ct2_reg_init()
275 ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_reg_init()
276 ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_reg_init()
281 ioc->ioc_regs.ioc_sem_reg = (rb + CT2_HOST_SEM0_REG); in bfa_ioc_ct2_reg_init()
282 ioc->ioc_regs.ioc_usage_sem_reg = (rb + CT2_HOST_SEM1_REG); in bfa_ioc_ct2_reg_init()
283 ioc->ioc_regs.ioc_init_sem_reg = (rb + CT2_HOST_SEM2_REG); in bfa_ioc_ct2_reg_init()
284 ioc->ioc_regs.ioc_usage_reg = (rb + CT2_BFA_FW_USE_COUNT); in bfa_ioc_ct2_reg_init()
285 ioc->ioc_regs.ioc_fail_sync = (rb + CT2_BFA_IOC_FAIL_SYNC); in bfa_ioc_ct2_reg_init()
290 ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START); in bfa_ioc_ct2_reg_init()
296 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct2_reg_init()
307 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
313 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
324 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
327 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
340 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
343 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
364 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
564 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_poweron() local
567 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_ioc_ct2_poweron()
570 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_ioc_ct2_poweron()
576 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_ioc_ct2_poweron()
578 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_ioc_ct2_poweron()
582 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode mode) in bfa_ioc_ct_pll_init() argument
597 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
599 __APP_EMS_CHANNEL_SEL, (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
601 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
602 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
604 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
605 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
606 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
607 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
608 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
609 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
610 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
611 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
613 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
615 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
617 __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
619 __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
620 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
622 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
623 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
624 writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
625 writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
628 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
629 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
631 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
633 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
636 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
637 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
640 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
642 r32 = readl((rb + MBIST_STAT_REG)); in bfa_ioc_ct_pll_init()
643 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
648 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
655 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
659 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
665 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
667 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
672 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
673 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_sclk_init()
675 r32 = readl((rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
676 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG)); in bfa_ioc_ct2_sclk_init()
681 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
684 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
693 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
700 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
704 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
709 r32 = readl((rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
710 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
715 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
716 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
721 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
724 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
733 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
737 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
739 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_mem_init()
742 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
744 writel(0, (rb + CT2_MBIST_CTL_REG)); in bfa_ioc_ct2_mem_init()
748 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
752 rb + CT2_CSI_MAC_CONTROL_REG(0)); in bfa_ioc_ct2_mac_reset()
754 rb + CT2_CSI_MAC_CONTROL_REG(1)); in bfa_ioc_ct2_mac_reset()
758 bfa_ioc_ct2_enable_flash(void __iomem *rb) in bfa_ioc_ct2_enable_flash() argument
762 r32 = readl((rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_enable_flash()
763 writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG)); in bfa_ioc_ct2_enable_flash()
764 r32 = readl((rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_enable_flash()
765 writel(r32 | 1, (rb + PSS_GPIO_OE_REG)); in bfa_ioc_ct2_enable_flash()
775 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
779 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
787 bfa_ioc_ct2_nfc_halt(void __iomem *rb) in bfa_ioc_ct2_nfc_halt() argument
791 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halt()
793 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_nfc_halt()
797 WARN_ON(!bfa_ioc_ct2_nfc_halted(rb)); in bfa_ioc_ct2_nfc_halt()
801 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
806 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
808 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
817 bfa_ioc_ct2_clk_reset(void __iomem *rb) in bfa_ioc_ct2_clk_reset() argument
821 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_clk_reset()
822 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_clk_reset()
827 r32 = readl((rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
829 (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
831 r32 = readl((rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
833 (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_clk_reset()
838 bfa_ioc_ct2_nfc_clk_reset(void __iomem *rb) in bfa_ioc_ct2_nfc_clk_reset() argument
842 r32 = readl((rb + PSS_CTL_REG)); in bfa_ioc_ct2_nfc_clk_reset()
844 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct2_nfc_clk_reset()
846 writel(__RESET_AND_START_SCLK_LCLK_PLLS, rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_nfc_clk_reset()
849 r32 = readl(rb + CT2_NFC_FLASH_STS_REG); in bfa_ioc_ct2_nfc_clk_reset()
857 r32 = readl(rb + CT2_NFC_FLASH_STS_REG); in bfa_ioc_ct2_nfc_clk_reset()
864 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_nfc_clk_reset()
869 bfa_ioc_ct2_wait_till_nfc_running(void __iomem *rb) in bfa_ioc_ct2_wait_till_nfc_running() argument
874 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_wait_till_nfc_running()
875 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_wait_till_nfc_running()
877 r32 = readl(rb + CT2_NFC_STS_REG); in bfa_ioc_ct2_wait_till_nfc_running()
883 r32 = readl(rb + CT2_NFC_STS_REG); in bfa_ioc_ct2_wait_till_nfc_running()
888 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode mode) in bfa_ioc_ct2_pll_init() argument
892 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
898 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
899 bfa_ioc_ct2_enable_flash(rb); in bfa_ioc_ct2_pll_init()
901 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
903 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
904 bfa_ioc_ct2_enable_flash(rb); in bfa_ioc_ct2_pll_init()
907 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
912 bfa_ioc_ct2_wait_till_nfc_running(rb); in bfa_ioc_ct2_pll_init()
914 bfa_ioc_ct2_nfc_clk_reset(rb); in bfa_ioc_ct2_pll_init()
916 bfa_ioc_ct2_nfc_halt(rb); in bfa_ioc_ct2_pll_init()
918 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
919 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
920 bfa_ioc_ct2_clk_reset(rb); in bfa_ioc_ct2_pll_init()
932 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_pll_init()
933 writel((r32 & 0xfbffffff), (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_pll_init()
940 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
941 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); in bfa_ioc_ct2_pll_init()
944 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
946 r32 = readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
948 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
949 readl((rb + CT2_LPU0_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
951 r32 = readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
953 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
954 readl((rb + CT2_LPU1_HOSTFN_CMD_STAT)); in bfa_ioc_ct2_pll_init()
958 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
960 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); in bfa_ioc_ct2_pll_init()
961 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); in bfa_ioc_ct2_pll_init()