214 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
216 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
227 		if ((NCR5380_read(reg1) & bit1) == val1)  in NCR5380_poll_politely2()
229 		if ((NCR5380_read(reg2) & bit2) == val2)  in NCR5380_poll_politely2()
297 	status = NCR5380_read(STATUS_REG);  in NCR5380_print()
298 	mr = NCR5380_read(MODE_REG);  in NCR5380_print()
299 	icr = NCR5380_read(INITIATOR_COMMAND_REG);  in NCR5380_print()
300 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_print()
347 	status = NCR5380_read(STATUS_REG);  in NCR5380_print_phase()
444 		NCR5380_read(STATUS_REG);  in NCR5380_init()
473 	for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {  in NCR5380_maybe_reset_bus()
766 			if ((NCR5380_read(BUS_AND_STATUS_REG) &  in NCR5380_dma_complete()
769 				saved_data = NCR5380_read(INPUT_DATA_REG);  in NCR5380_dma_complete()
783 	if ((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | BASR_ACK)) ==  in NCR5380_dma_complete()
786 		       NCR5380_read(BUS_AND_STATUS_REG));  in NCR5380_dma_complete()
795 	NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_dma_complete()
808 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {  in NCR5380_dma_complete()
872 	basr = NCR5380_read(BUS_AND_STATUS_REG);  in NCR5380_intr()
874 		unsigned char mr = NCR5380_read(MODE_REG);  in NCR5380_intr()
875 		unsigned char sr = NCR5380_read(STATUS_REG);  in NCR5380_intr()
893 				NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
895 		} else if ((NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_mask) &&  in NCR5380_intr()
899 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
911 			NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_intr()
1012 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE)) {  in NCR5380_select()
1033 	if ((NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST) ||  in NCR5380_select()
1034 	    (NCR5380_read(CURRENT_SCSI_DATA_REG) & hostdata->id_higher_mask) ||  in NCR5380_select()
1035 	    (NCR5380_read(INITIATOR_COMMAND_REG) & ICR_ARBITRATION_LOST)) {  in NCR5380_select()
1062 	if (!(NCR5380_read(MODE_REG) & MR_ARBITRATE))  in NCR5380_select()
1137 	if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {  in NCR5380_select()
1276 		if ((NCR5380_read(STATUS_REG) & PHASE_MASK) != p) {  in NCR5380_transfer_pio()
1286 			*d = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_transfer_pio()
1346 	tmp = NCR5380_read(STATUS_REG);  in NCR5380_transfer_pio()
1376 	              PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK));  in do_reset()
1380 	(void)NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in do_reset()
1418 	tmp = NCR5380_read(STATUS_REG) & PHASE_MASK;  in do_abort()
1481 	if ((tmp = (NCR5380_read(STATUS_REG) & PHASE_MASK)) != p) {  in NCR5380_transfer_dma()
1601 	    (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {  in NCR5380_transfer_dma()
1623 			    (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) {  in NCR5380_transfer_dma()
1626 					d[c] = NCR5380_read(INPUT_DATA_REG);  in NCR5380_transfer_dma()
1634 		} else if (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH) {  in NCR5380_transfer_dma()
1678 		tmp = NCR5380_read(STATUS_REG);  in NCR5380_information_transfer()
1715 				while (NCR5380_read(STATUS_REG) & SR_REQ)  in NCR5380_information_transfer()
2004 			    !(NCR5380_read(STATUS_REG) & SR_BSY)) {  in NCR5380_information_transfer()
2040 	target_mask = NCR5380_read(CURRENT_SCSI_DATA_REG) & ~(hostdata->id_mask);  in NCR5380_reselect()
2071 		if ((NCR5380_read(STATUS_REG) & (SR_BSY | SR_SEL)) == 0)  in NCR5380_reselect()
2084 	msg[0] = NCR5380_read(CURRENT_SCSI_DATA_REG);  in NCR5380_reselect()