Lines Matching +full:tegra20 +full:- +full:ahb
1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2010-2019, NVIDIA Corporation.
21 /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */
58 * RTC hardware is busy when it is updating its values over AHB once every
64 return readl(info->base + TEGRA_RTC_REG_BUSY) & 1; in tegra_rtc_check_busy()
74 * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this
85 * updated seconds+msec registers to AHB side. in tegra_rtc_wait_while_busy()
88 if (!retries--) in tegra_rtc_wait_while_busy()
99 return -ETIMEDOUT; in tegra_rtc_wait_while_busy()
112 spin_lock_irqsave(&info->lock, flags); in tegra_rtc_read_time()
114 readl(info->base + TEGRA_RTC_REG_MILLI_SECONDS); in tegra_rtc_read_time()
115 sec = readl(info->base + TEGRA_RTC_REG_SHADOW_SECONDS); in tegra_rtc_read_time()
117 spin_unlock_irqrestore(&info->lock, flags); in tegra_rtc_read_time()
140 writel(sec, info->base + TEGRA_RTC_REG_SECONDS); in tegra_rtc_set_time()
143 readl(info->base + TEGRA_RTC_REG_SECONDS)); in tegra_rtc_set_time()
153 sec = readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0); in tegra_rtc_read_alarm()
157 alarm->enabled = 0; in tegra_rtc_read_alarm()
160 alarm->enabled = 1; in tegra_rtc_read_alarm()
161 rtc_time64_to_tm(sec, &alarm->time); in tegra_rtc_read_alarm()
164 value = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_read_alarm()
165 alarm->pending = (value & TEGRA_RTC_INTR_STATUS_SEC_ALARM0) != 0; in tegra_rtc_read_alarm()
177 spin_lock_irqsave(&info->lock, flags); in tegra_rtc_alarm_irq_enable()
180 status = readl(info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_alarm_irq_enable()
186 writel(status, info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_alarm_irq_enable()
188 spin_unlock_irqrestore(&info->lock, flags); in tegra_rtc_alarm_irq_enable()
198 if (alarm->enabled) in tegra_rtc_set_alarm()
199 sec = rtc_tm_to_time64(&alarm->time); in tegra_rtc_set_alarm()
204 writel(sec, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); in tegra_rtc_set_alarm()
206 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); in tegra_rtc_set_alarm()
211 dev_vdbg(dev, "alarm set as %u, %ptR\n", sec, &alarm->time); in tegra_rtc_set_alarm()
223 if (!dev || !dev->driver) in tegra_rtc_proc()
238 status = readl(info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_irq_handler()
243 spin_lock(&info->lock); in tegra_rtc_irq_handler()
244 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_irq_handler()
245 writel(status, info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_irq_handler()
246 spin_unlock(&info->lock); in tegra_rtc_irq_handler()
257 rtc_update_irq(info->rtc, 1, events); in tegra_rtc_irq_handler()
272 { .compatible = "nvidia,tegra20-rtc", },
282 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); in tegra_rtc_probe()
284 return -ENOMEM; in tegra_rtc_probe()
286 info->base = devm_platform_ioremap_resource(pdev, 0); in tegra_rtc_probe()
287 if (IS_ERR(info->base)) in tegra_rtc_probe()
288 return PTR_ERR(info->base); in tegra_rtc_probe()
294 info->irq = ret; in tegra_rtc_probe()
296 info->rtc = devm_rtc_allocate_device(&pdev->dev); in tegra_rtc_probe()
297 if (IS_ERR(info->rtc)) in tegra_rtc_probe()
298 return PTR_ERR(info->rtc); in tegra_rtc_probe()
300 info->rtc->ops = &tegra_rtc_ops; in tegra_rtc_probe()
301 info->rtc->range_max = U32_MAX; in tegra_rtc_probe()
303 info->clk = devm_clk_get(&pdev->dev, NULL); in tegra_rtc_probe()
304 if (IS_ERR(info->clk)) in tegra_rtc_probe()
305 return PTR_ERR(info->clk); in tegra_rtc_probe()
307 ret = clk_prepare_enable(info->clk); in tegra_rtc_probe()
312 info->pdev = pdev; in tegra_rtc_probe()
313 spin_lock_init(&info->lock); in tegra_rtc_probe()
318 writel(0, info->base + TEGRA_RTC_REG_SECONDS_ALARM0); in tegra_rtc_probe()
319 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_probe()
320 writel(0, info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_probe()
322 device_init_wakeup(&pdev->dev, 1); in tegra_rtc_probe()
324 ret = devm_request_irq(&pdev->dev, info->irq, tegra_rtc_irq_handler, in tegra_rtc_probe()
325 IRQF_TRIGGER_HIGH, dev_name(&pdev->dev), in tegra_rtc_probe()
326 &pdev->dev); in tegra_rtc_probe()
328 dev_err(&pdev->dev, "failed to request interrupt: %d\n", ret); in tegra_rtc_probe()
332 ret = devm_rtc_register_device(info->rtc); in tegra_rtc_probe()
336 dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n"); in tegra_rtc_probe()
341 clk_disable_unprepare(info->clk); in tegra_rtc_probe()
349 clk_disable_unprepare(info->clk); in tegra_rtc_remove()
360 writel(0xffffffff, info->base + TEGRA_RTC_REG_INTR_STATUS); in tegra_rtc_suspend()
362 info->base + TEGRA_RTC_REG_INTR_MASK); in tegra_rtc_suspend()
365 readl(info->base + TEGRA_RTC_REG_SECONDS_ALARM0)); in tegra_rtc_suspend()
368 device_may_wakeup(dev), info->irq); in tegra_rtc_suspend()
372 enable_irq_wake(info->irq); in tegra_rtc_suspend()
386 disable_irq_wake(info->irq); in tegra_rtc_resume()
396 dev_vdbg(&pdev->dev, "disabling interrupts\n"); in tegra_rtc_shutdown()
397 tegra_rtc_alarm_irq_enable(&pdev->dev, 0); in tegra_rtc_shutdown()