61 static void mpfs_rtc_start(struct mpfs_rtc_dev *rtcdev)  in mpfs_rtc_start()  argument
65 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_start()
68 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_start()
71 static void mpfs_rtc_clear_irq(struct mpfs_rtc_dev *rtcdev)  in mpfs_rtc_clear_irq()  argument
73 	u32 val = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_clear_irq()
77 	writel(val, rtcdev->base + CONTROL_REG);  in mpfs_rtc_clear_irq()
83 	(void)readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_clear_irq()
88 	struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);  in mpfs_rtc_readtime()  local
91 	time = readl(rtcdev->base + DATETIME_LOWER_REG);  in mpfs_rtc_readtime()
92 	time |= ((u64)readl(rtcdev->base + DATETIME_UPPER_REG) & DATETIME_UPPER_MASK) << 32;  in mpfs_rtc_readtime()
100 	struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);  in mpfs_rtc_settime()  local
107 	writel((u32)time, rtcdev->base + DATETIME_LOWER_REG);  in mpfs_rtc_settime()
108 	writel((u32)(time >> 32) & DATETIME_UPPER_MASK, rtcdev->base + DATETIME_UPPER_REG);  in mpfs_rtc_settime()
110 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_settime()
113 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_settime()
116 				false, rtcdev->base + CONTROL_REG);  in mpfs_rtc_settime()
121 	mpfs_rtc_start(rtcdev);  in mpfs_rtc_settime()
128 	struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);  in mpfs_rtc_readalarm()  local
129 	u32 mode = readl(rtcdev->base + MODE_REG);  in mpfs_rtc_readalarm()
134 	time = (u64)readl(rtcdev->base + ALARM_LOWER_REG) << 32;  in mpfs_rtc_readalarm()
135 	time |= (readl(rtcdev->base + ALARM_UPPER_REG) & ALARM_UPPER_MASK);  in mpfs_rtc_readalarm()
143 	struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);  in mpfs_rtc_setalarm()  local
148 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
150 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
154 	writel((u32)time, rtcdev->base + ALARM_LOWER_REG);  in mpfs_rtc_setalarm()
155 	writel((u32)(time >> 32) & ALARM_UPPER_MASK, rtcdev->base + ALARM_UPPER_REG);  in mpfs_rtc_setalarm()
158 	writel(GENMASK(31, 0), rtcdev->base + COMPARE_LOWER_REG);  in mpfs_rtc_setalarm()
159 	writel(GENMASK(29, 0), rtcdev->base + COMPARE_UPPER_REG);  in mpfs_rtc_setalarm()
162 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
163 	mode = readl(rtcdev->base + MODE_REG);  in mpfs_rtc_setalarm()
172 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_setalarm()
173 	writel(mode, rtcdev->base + MODE_REG);  in mpfs_rtc_setalarm()
180 	struct mpfs_rtc_dev *rtcdev = dev_get_drvdata(dev);  in mpfs_rtc_alarm_irq_enable()  local
183 	ctrl = readl(rtcdev->base + CONTROL_REG);  in mpfs_rtc_alarm_irq_enable()
191 	writel(ctrl, rtcdev->base + CONTROL_REG);  in mpfs_rtc_alarm_irq_enable()
198 	struct mpfs_rtc_dev *rtcdev = dev;  in mpfs_rtc_wakeup_irq_handler()  local
200 	mpfs_rtc_clear_irq(rtcdev);  in mpfs_rtc_wakeup_irq_handler()
202 	rtc_update_irq(rtcdev->rtc, 1, RTC_IRQF | RTC_AF);  in mpfs_rtc_wakeup_irq_handler()
217 	struct mpfs_rtc_dev *rtcdev;  in mpfs_rtc_probe()  local
222 	rtcdev = devm_kzalloc(&pdev->dev, sizeof(struct mpfs_rtc_dev), GFP_KERNEL);  in mpfs_rtc_probe()
223 	if (!rtcdev)  in mpfs_rtc_probe()
226 	platform_set_drvdata(pdev, rtcdev);  in mpfs_rtc_probe()
228 	rtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);  in mpfs_rtc_probe()
229 	if (IS_ERR(rtcdev->rtc))  in mpfs_rtc_probe()
230 		return PTR_ERR(rtcdev->rtc);  in mpfs_rtc_probe()
232 	rtcdev->rtc->ops = &mpfs_rtc_ops;  in mpfs_rtc_probe()
235 	rtcdev->rtc->range_max = GENMASK_ULL(42, 0);  in mpfs_rtc_probe()
241 	rtcdev->base = devm_platform_ioremap_resource(pdev, 0);  in mpfs_rtc_probe()
242 	if (IS_ERR(rtcdev->base)) {  in mpfs_rtc_probe()
244 		return PTR_ERR(rtcdev->base);  in mpfs_rtc_probe()
253 			       dev_name(&pdev->dev), rtcdev);  in mpfs_rtc_probe()
266 	writel(prescaler, rtcdev->base + PRESCALER_REG);  in mpfs_rtc_probe()
274 	return devm_rtc_register_device(rtcdev->rtc);  in mpfs_rtc_probe()