23 #define JZ_REG_RTC_CTRL		0x00
24 #define JZ_REG_RTC_SEC		0x04
25 #define JZ_REG_RTC_SEC_ALARM	0x08
26 #define JZ_REG_RTC_REGULATOR	0x0C
27 #define JZ_REG_RTC_HIBERNATE	0x20
28 #define JZ_REG_RTC_WAKEUP_FILTER	0x24
29 #define JZ_REG_RTC_RESET_COUNTER	0x28
30 #define JZ_REG_RTC_SCRATCHPAD	0x34
31 #define JZ_REG_RTC_CKPCR	0x40
34 #define JZ_REG_RTC_WENR	0x3C
43 #define JZ_RTC_CTRL_ENABLE	BIT(0)
46 #define JZ_RTC_WENR_MAGIC	0xA55A
48 #define JZ_RTC_WAKEUP_FILTER_MASK	0x0000FFE0
49 #define JZ_RTC_RESET_COUNTER_MASK	0x00000FE0
83 				  ctrl & JZ_RTC_CTRL_WRDY, 0, 1000);  in jz4740_rtc_wait_write_ready()
92 	if (ret != 0)  in jz4780_rtc_enable_write()
98 				  ctrl & JZ_RTC_WENR_WEN, 0, 1000);  in jz4780_rtc_enable_write()
104 	int ret = 0;  in jz4740_rtc_reg_write()
108 	if (ret == 0)  in jz4740_rtc_reg_write()
110 	if (ret == 0)  in jz4740_rtc_reg_write()
148 	if (jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD) != 0x12345678)  in jz4740_rtc_read_time()
163 	if (timeout == 0)  in jz4740_rtc_read_time()
168 	return 0;  in jz4740_rtc_read_time()
180 	return jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);  in jz4740_rtc_set_time()
198 	return 0;  in jz4740_rtc_read_alarm()
233 	unsigned long events = 0;  in jz4740_rtc_irq()
286 	 * Range is 0 to 2 sec if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
297 	 * Range is 0 to 125 ms if RTC is clocked at 32 kHz.  in jz4740_rtc_set_wakeup_params()
320 	jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CKPCR, 0);  in jz4740_rtc_clk32k_disable()
354 	irq = platform_get_irq(pdev, 0);  in jz4740_rtc_probe()
355 	if (irq < 0)  in jz4740_rtc_probe()
358 	rtc->base = devm_platform_ioremap_resource(pdev, 0);  in jz4740_rtc_probe()
394 	ret = devm_request_irq(dev, irq, jz4740_rtc_irq, 0,  in jz4740_rtc_probe()
410 						  &jz4740_rtc_clk32k_ops, 0);  in jz4740_rtc_probe()
424 	return 0;  in jz4740_rtc_probe()