Lines Matching +full:0 +full:x4080

15 #define MT8183_SW_RSTN			0x0
16 #define MT8183_SW_RSTN_BIT		BIT(0)
17 #define MT8183_SCP_TO_HOST		0x1C
18 #define MT8183_SCP_IPC_INT_BIT		BIT(0)
20 #define MT8183_HOST_TO_SCP		0x28
21 #define MT8183_HOST_IPC_INT_BIT		BIT(0)
22 #define MT8183_WDT_CFG			0x84
23 #define MT8183_SCP_CLK_SW_SEL		0x4000
24 #define MT8183_SCP_CLK_DIV_SEL		0x4024
25 #define MT8183_SCP_SRAM_PDN		0x402C
26 #define MT8183_SCP_L1_SRAM_PD		0x4080
27 #define MT8183_SCP_TCM_TAIL_SRAM_PD	0x4094
29 #define MT8183_SCP_CACHE_SEL(x)		(0x14000 + (x) * 0x3000)
30 #define MT8183_SCP_CACHE_CON		MT8183_SCP_CACHE_SEL(0)
35 #define MT8186_SCP_L1_SRAM_PD_P1	0x40B0
36 #define MT8186_SCP_L1_SRAM_PD_p2	0x40B4
38 #define MT8192_L2TCM_SRAM_PD_0		0x10C0
39 #define MT8192_L2TCM_SRAM_PD_1		0x10C4
40 #define MT8192_L2TCM_SRAM_PD_2		0x10C8
41 #define MT8192_L1TCM_SRAM_PDN		0x102C
42 #define MT8192_CPU0_SRAM_PD		0x1080
44 #define MT8192_SCP2APMCU_IPC_SET	0x4080
45 #define MT8192_SCP2APMCU_IPC_CLR	0x4084
46 #define MT8192_SCP_IPC_INT_BIT		BIT(0)
47 #define MT8192_SCP2SPM_IPC_CLR		0x4094
48 #define MT8192_GIPC_IN_SET		0x4098
49 #define MT8192_HOST_IPC_INT_BIT		BIT(0)
52 #define MT8192_CORE0_SW_RSTN_CLR	0x10000
53 #define MT8192_CORE0_SW_RSTN_SET	0x10004
54 #define MT8192_CORE0_MEM_ATT_PREDEF	0x10008
55 #define MT8192_CORE0_WDT_IRQ		0x10030
56 #define MT8192_CORE0_WDT_CFG		0x10034
58 #define MT8195_SYS_STATUS		0x4004
64 #define MT8195_CPU1_SRAM_PD			0x1084
65 #define MT8195_SSHUB2APMCU_IPC_SET		0x4088
66 #define MT8195_SSHUB2APMCU_IPC_CLR		0x408C
67 #define MT8195_CORE1_SW_RSTN_CLR		0x20000
68 #define MT8195_CORE1_SW_RSTN_SET		0x20004
69 #define MT8195_CORE1_MEM_ATT_PREDEF		0x20008
70 #define MT8195_CORE1_WDT_IRQ			0x20030
71 #define MT8195_CORE1_WDT_CFG			0x20034
73 #define MT8195_SEC_CTRL				0x85000
76 #define MT8195_L2TCM_OFFSET_RANGE_0_LOW		0x850b0
77 #define MT8195_L2TCM_OFFSET_RANGE_0_HIGH	0x850b4
78 #define MT8195_L2TCM_OFFSET			0x850d0