29 #define IMX7D_SRC_SCR			0x0C
33 #define IMX7D_SW_M4C_NON_SCLR_RST	BIT(0)
47 #define IMX8M_GPR22			0x58
48 #define IMX8M_GPR22_CM7_CPUWAIT		BIT(0)
50 /* Address: 0x020D8000 */
51 #define IMX6SX_SRC_SCR			0x00
67 #define IMX_SIP_RPROC			0xC2000005
68 #define IMX_SIP_RPROC_START		0x00
69 #define IMX_SIP_RPROC_STARTED		0x01
70 #define IMX_SIP_RPROC_STOP		0x02
91 #define ATT_CORE_MASK   0xffff
123 	{ 0x0FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
126 	{ 0x1FFC0000, 0x201C0000, 0x00040000, ATT_OWN | ATT_IOMEM },
129 	{ 0x20000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
132 	{ 0x30000000, 0x20200000, 0x00040000, ATT_OWN | ATT_IOMEM },
135 	{ 0x80000000, 0x80000000, 0x10000000, 0 },
136 	{ 0x90000000, 0x80000000, 0x10000000, 0 },
138 	{ 0xC0000000, 0xC0000000, 0x10000000, 0 },
139 	{ 0xD0000000, 0xC0000000, 0x10000000, 0 },
144 	{ 0x08000000, 0x08000000, 0x10000000, 0},
146 	{ 0x1FFE0000, 0x34FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
147 	{ 0x1FFE0000, 0x38FE0000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
149 	{ 0x20000000, 0x35000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(0)},
150 	{ 0x20000000, 0x39000000, 0x00020000, ATT_OWN | ATT_IOMEM | ATT_CORE(1)},
152 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
156 	{ 0x08000000, 0x08000000, 0x10000000, 0 },
158 	{ 0x1FFE0000, 0x34FE0000, 0x00040000, ATT_OWN | ATT_IOMEM },
160 	{ 0x21000000, 0x00100000, 0x00018000, 0 },
162 	{ 0x21100000, 0x00100000, 0x00040000, 0 },
164 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
170 	{ 0x00000000, 0x007E0000, 0x00020000, ATT_OWN | ATT_IOMEM },
172 	{ 0x00180000, 0x00180000, 0x00009000, 0 },
174 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
176 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
178 	{ 0x00940000, 0x00940000, 0x00050000, 0 },
180 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
182 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
184 	{ 0x20000000, 0x00800000, 0x00020000, ATT_OWN | ATT_IOMEM },
186 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
188 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
190 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
192 	{ 0x20240000, 0x00940000, 0x00040000, ATT_OWN },
194 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
200 	{ 0x00000000, 0x007e0000, 0x00020000, ATT_IOMEM},
202 	{ 0x00180000, 0x00180000, 0x00008000, 0 },
204 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
206 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
208 	{ 0x08000000, 0x08000000, 0x08000000, 0 },
210 	{ 0x10000000, 0x40000000, 0x0FFE0000, 0 },
212 	{ 0x1FFE0000, 0x007E0000, 0x00040000, ATT_OWN  | ATT_IOMEM},
214 	{ 0x20180000, 0x00180000, 0x00008000, ATT_OWN },
216 	{ 0x20200000, 0x00900000, 0x00020000, ATT_OWN },
218 	{ 0x20220000, 0x00920000, 0x00020000, ATT_OWN },
220 	{ 0x40000000, 0x40000000, 0x80000000, 0 },
224 	{0x1FFC0000, 0x1FFC0000, 0xC0000, ATT_OWN},
225 	{0x21000000, 0x21000000, 0x10000, ATT_OWN},
226 	{0x80000000, 0x80000000, 0x60000000, 0}
230 	{0x1FFD0000, 0x1FFD0000, 0x30000, ATT_OWN},
231 	{0x20000000, 0x20000000, 0x10000, ATT_OWN},
232 	{0x2F000000, 0x2F000000, 0x20000, ATT_OWN},
233 	{0x2F020000, 0x2F020000, 0x20000, ATT_OWN},
234 	{0x60000000, 0x60000000, 0x40000000, 0}
240 	{ 0x00000000, 0x00180000, 0x00008000, 0 },
242 	{ 0x00180000, 0x00180000, 0x00008000, ATT_OWN },
244 	{ 0x00900000, 0x00900000, 0x00020000, 0 },
246 	{ 0x00920000, 0x00920000, 0x00020000, 0 },
248 	{ 0x00940000, 0x00940000, 0x00008000, 0 },
250 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
252 	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
255 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
257 	{ 0x20200000, 0x00900000, 0x00020000, 0 },
259 	{ 0x20220000, 0x00920000, 0x00020000, 0 },
261 	{ 0x20240000, 0x00940000, 0x00008000, 0 },
263 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
269 	{ 0x00000000, 0x007F8000, 0x00008000, ATT_IOMEM },
271 	{ 0x00180000, 0x008F8000, 0x00004000, 0 },
273 	{ 0x00180000, 0x008FC000, 0x00004000, 0 },
275 	{ 0x1FFF8000, 0x007F8000, 0x00008000, ATT_OWN | ATT_IOMEM },
277 	{ 0x10000000, 0x80000000, 0x0FFF8000, 0 },
280 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN | ATT_IOMEM },
282 	{ 0x208F8000, 0x008F8000, 0x00004000, 0 },
284 	{ 0x80000000, 0x80000000, 0x60000000, 0 },
390 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_START, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_start()
430 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STOP, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_stop()
457 	for (i = 0; i < dcfg->att_size; i++) {  in imx_rproc_da_to_sys()
462 		 * i.MX8QM has dual general M4_[0,1] cores, M4_0's own entries  in imx_rproc_da_to_sys()
463 		 * has "ATT_CORE(0) & BIT(0)" true, M4_1's own entries has  in imx_rproc_da_to_sys()
477 			return 0;  in imx_rproc_da_to_sys()
481 	dev_warn(priv->dev, "Translation failed: da = 0x%llx len = 0x%zx\n",  in imx_rproc_da_to_sys()
493 	if (len == 0)  in imx_rproc_da_to_va()
503 	for (i = 0; i < IMX_RPROC_MEM_MAX; i++) {  in imx_rproc_da_to_va()
513 	dev_dbg(&rproc->dev, "da = 0x%llx len = 0x%zx va = 0x%p\n",  in imx_rproc_da_to_va()
536 	return 0;  in imx_rproc_mem_alloc()
545 	return 0;  in imx_rproc_mem_release()
558 	of_phandle_iterator_init(&it, np, "memory-region", NULL, 0);  in imx_rproc_prepare()
559 	while (of_phandle_iterator_next(&it) == 0) {  in imx_rproc_prepare()
595 	return  0;  in imx_rproc_prepare()
606 	return 0;  in imx_rproc_parse_fw()
627 	if (err < 0)  in imx_rproc_kick()
650 	return 0;  in imx_rproc_detach()
698 	int a, b = 0, err, nph;  in imx_rproc_addr_init()
701 	for (a = 0; a < dcfg->att_size; a++) {  in imx_rproc_addr_init()
727 	if (nph <= 0)  in imx_rproc_addr_init()
728 		return 0;  in imx_rproc_addr_init()
731 	for (a = 0; a < nph; a++) {  in imx_rproc_addr_init()
743 		err = of_address_to_resource(node, 0, &res);  in imx_rproc_addr_init()
770 	return 0;  in imx_rproc_addr_init()
779 	return 0;  in imx_rproc_notified_idr_cb()
815 		return 0;  in imx_rproc_xtr_mbox_init()
818 		return 0;  in imx_rproc_xtr_mbox_init()
839 	return 0;  in imx_rproc_xtr_mbox_init()
881 		return 0;  in imx_rproc_partition_notify()
887 	return 0;  in imx_rproc_partition_notify()
903 		return 0;  in imx_rproc_attach_pd()
906 	return ret < 0 ? ret : 0;  in imx_rproc_attach_pd()
923 		return 0;  in imx_rproc_detect_mode()
925 		arm_smccc_smc(IMX_SIP_RPROC, IMX_SIP_RPROC_STARTED, 0, 0, 0, 0, 0, 0, &res);  in imx_rproc_detect_mode()
928 		return 0;  in imx_rproc_detect_mode()
942 			priv->core_index = 0;  in imx_rproc_detect_mode()
983 		return 0;  in imx_rproc_detect_mode()
1010 			return 0;  in imx_rproc_detect_mode()
1023 	return 0;  in imx_rproc_detect_mode()
1034 		return 0;  in imx_rproc_clk_enable()
1052 	return 0;  in imx_rproc_clk_enable()
1155 	return 0;  in imx_rproc_probe()