15 #define RTQ2208_REG_GLOBAL_INT1			0x12
16 #define RTQ2208_REG_FLT_RECORDBUCK_CB		0x18
17 #define RTQ2208_REG_GLOBAL_INT1_MASK		0x1D
18 #define RTQ2208_REG_FLT_MASKBUCK_CB		0x1F
19 #define RTQ2208_REG_BUCK_C_CFG0			0x32
20 #define RTQ2208_REG_BUCK_B_CFG0			0x42
21 #define RTQ2208_REG_BUCK_A_CFG0			0x52
22 #define RTQ2208_REG_BUCK_D_CFG0			0x62
23 #define RTQ2208_REG_BUCK_G_CFG0			0x72
24 #define RTQ2208_REG_BUCK_F_CFG0			0x82
25 #define RTQ2208_REG_BUCK_E_CFG0			0x92
26 #define RTQ2208_REG_BUCK_H_CFG0			0xA2
27 #define RTQ2208_REG_LDO1_CFG			0xB1
28 #define RTQ2208_REG_LDO2_CFG			0xC1
29 #define RTQ2208_REG_LDO_DVS_CTRL		0xD0
32 #define RTQ2208_BUCK_NR_MTP_SEL_MASK		GENMASK(7, 0)
33 #define RTQ2208_BUCK_EN_NR_MTP_SEL0_MASK	BIT(0)
36 #define RTQ2208_BUCK_RSPDN_MASK			GENMASK(2, 0)
39 #define RTQ2208_BUCK_EN_STR_MASK		BIT(0)
41 #define RTQ2208_EN_DIS_MASK			BIT(0)
42 #define RTQ2208_BUCK_RAMP_SEL_MASK		GENMASK(2, 0)
43 #define RTQ2208_HD_INT_MASK			BIT(0)
61 	RTQ2208_BUCK_B = 0,
75 	RTQ2208_AUTO_MODE = 0,
136 	unsigned int sel = 0, val;  in rtq2208_set_ramp_delay()
144 	 * fls(ramp_delay) - 1: doing LSB shift, let it starts from 0  in rtq2208_set_ramp_delay()
154 	 * For example, if I would like to select 16mv, the fls(ramp_delay) - 1 will be 0b010,  in rtq2208_set_ramp_delay()
155 	 * and I need to use 0b111 - sel to do the shifting  in rtq2208_set_ramp_delay()
180 	return regmap_update_bits(rdev->regmap, rdesc->suspend_config_reg, rdesc->suspend_enable_mask, 0);  in rtq2208_set_suspend_disable()
267 	unsigned char buck_clr_masks[5] = {0x33, 0x33, 0x33, 0x33, 0x33},  in rtq2208_init_irq_mask()
268 		      sts_clr_masks[2] = {0xE7, 0xF7}, sts_masks[2] = {0xE6, 0xF6};  in rtq2208_init_irq_mask()
293 	int ret = 0, i, uv_bit, ov_bit;  in rtq2208_irq_handler()
322 	for (i = 0; i < RTQ2208_LDO_MAX; i++) {  in rtq2208_irq_handler()
328 		uv_bit = (i & 1) ? 4 : 0;  in rtq2208_irq_handler()
367 	if (ret < 0)  in rtq2208_of_get_ldo_dvs_ability()
370 	for (i = 0; i < ARRAY_SIZE(rtq2208_ldo_match); i++) {  in rtq2208_of_get_ldo_dvs_ability()
396 	return 0;  in rtq2208_of_get_ldo_dvs_ability()
423 	REGULATOR_LINEAR_RANGE(400000, 0, 180, 5000),
459 	desc->enable_mask = mtp_sel ? MTP_SEL_MASK(1) : MTP_SEL_MASK(0);  in rtq2208_init_regulator_desc()
461 	desc->active_discharge_off = 0;  in rtq2208_init_regulator_desc()
504 	for (i = 0; i < n_regulator; i++) {  in rtq2208_parse_regulator_dt_data()
507 		rdesc[i] = devm_kcalloc(dev, 1, sizeof(*rdesc[0]), GFP_KERNEL);  in rtq2208_parse_regulator_dt_data()
523 	return 0;  in rtq2208_parse_regulator_dt_data()
528  * slave address 0x10: BUCK[BCA FGE]
529  * slave address 0x20: BUCK[BC FGHE]
530  * slave address 0x40: BUCK[C G]
537 		{1, 1, 0, 1, 1, 1, 0, 1, 1, 1},  in rtq2208_regulator_check()
539 		{1, 1, 0, 0, 1, 1, 1, 1, 1, 1},  in rtq2208_regulator_check()
541 		{0, 1, 0, 0, 0, 1, 0, 0, 1, 1},  in rtq2208_regulator_check()
546 	for (i = 0; i < RTQ2208_LDO_MAX; i++) {  in rtq2208_regulator_check()
556 	return 0;  in rtq2208_regulator_check()
562 	.max_register = 0xEF,
573 	int i, ret = 0, idx, n_regulator = 0;  in rtq2208_probe()
575 		     buck_masks[RTQ2208_BUCK_NUM_IRQ_REGS] = {0x33, 0x33, 0x33, 0x33, 0x33};  in rtq2208_probe()
600 	for (i = 0; i < n_regulator; i++) {  in rtq2208_probe()