Lines Matching +full:0 +full:xf00
54 .enable_mask = BIT(0), \
58 .qi = BIT(0), \
82 .vsel_mask = GENMASK(3, 0), \
107 .enable_mask = BIT(0), \
112 .qi = BIT(0), \
127 .vsel_mask = GENMASK(3, 0), \
155 .enable_mask = BIT(0), \
159 .qi = BIT(0), \
183 .vsel_mask = GENMASK(3, 0), \
208 .enable_mask = BIT(0), \
213 .qi = BIT(0), \
228 .vsel_mask = GENMASK(3, 0), \
240 static const unsigned int vdram2_selectors[] = { 0, 12 };
242 REGULATOR_LINEAR_RANGE(600000, 0, 10, 10000),
243 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
248 REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
249 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
250 REGULATOR_LINEAR_RANGE(2700000, 0, 10, 10000),
251 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
252 REGULATOR_LINEAR_RANGE(3100000, 0, 10, 10000),
255 static const unsigned int vibr_selectors[] = { 0, 1, 2, 4, 5, 9, 11, 13 };
257 REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
258 REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
259 REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
260 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
261 REGULATOR_LINEAR_RANGE(2000000, 0, 10, 10000),
262 REGULATOR_LINEAR_RANGE(2800000, 0, 10, 10000),
263 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
264 REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000),
270 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
271 REGULATOR_LINEAR_RANGE(3100000, 0, 10, 10000),
276 REGULATOR_LINEAR_RANGE(900000, 0, 10, 10000),
277 REGULATOR_LINEAR_RANGE(1000000, 0, 10, 10000),
278 REGULATOR_LINEAR_RANGE(1100000, 0, 10, 10000),
279 REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
280 REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
281 REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
282 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
287 REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
288 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
289 REGULATOR_LINEAR_RANGE(1900000, 0, 10, 10000),
294 REGULATOR_LINEAR_RANGE(2900000, 0, 10, 10000),
295 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
296 REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000),
299 static const unsigned int vcama_selectors[] = { 0, 7, 9, 10, 11, 12 };
301 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
302 REGULATOR_LINEAR_RANGE(2500000, 0, 10, 10000),
303 REGULATOR_LINEAR_RANGE(2700000, 0, 10, 10000),
304 REGULATOR_LINEAR_RANGE(2800000, 0, 10, 10000),
305 REGULATOR_LINEAR_RANGE(2900000, 0, 10, 10000),
306 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
311 REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000),
312 REGULATOR_LINEAR_RANGE(3400000, 0, 10, 10000),
313 REGULATOR_LINEAR_RANGE(3500000, 0, 10, 10000),
318 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
319 REGULATOR_LINEAR_RANGE(2900000, 0, 10, 10000),
320 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
321 REGULATOR_LINEAR_RANGE(3300000, 0, 10, 10000),
326 REGULATOR_LINEAR_RANGE(2800000, 0, 10, 10000),
327 REGULATOR_LINEAR_RANGE(3000000, 0, 10, 10000),
330 static const unsigned int mt6366_vmddr_selectors[] = { 0, 1, 2, 3, 4, 5, 6, 7, 9, 12 };
332 REGULATOR_LINEAR_RANGE(600000, 0, 10, 10000),
333 REGULATOR_LINEAR_RANGE(700000, 0, 10, 10000),
334 REGULATOR_LINEAR_RANGE(800000, 0, 10, 10000),
335 REGULATOR_LINEAR_RANGE(900000, 0, 10, 10000),
336 REGULATOR_LINEAR_RANGE(1000000, 0, 10, 10000),
337 REGULATOR_LINEAR_RANGE(1100000, 0, 10, 10000),
338 REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
339 REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
340 REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
341 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
345 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
347 REGULATOR_LINEAR_RANGE(600000, 0, 10, 10000),
348 REGULATOR_LINEAR_RANGE(700000, 0, 10, 10000),
349 REGULATOR_LINEAR_RANGE(800000, 0, 10, 10000),
350 REGULATOR_LINEAR_RANGE(900000, 0, 10, 10000),
351 REGULATOR_LINEAR_RANGE(1000000, 0, 10, 10000),
352 REGULATOR_LINEAR_RANGE(1100000, 0, 10, 10000),
353 REGULATOR_LINEAR_RANGE(1200000, 0, 10, 10000),
354 REGULATOR_LINEAR_RANGE(1300000, 0, 10, 10000),
355 REGULATOR_LINEAR_RANGE(1400000, 0, 10, 10000),
356 REGULATOR_LINEAR_RANGE(1500000, 0, 10, 10000),
357 REGULATOR_LINEAR_RANGE(1600000, 0, 10, 10000),
358 REGULATOR_LINEAR_RANGE(1700000, 0, 10, 10000),
359 REGULATOR_LINEAR_RANGE(1800000, 0, 10, 10000),
360 REGULATOR_LINEAR_RANGE(1900000, 0, 10, 10000),
361 REGULATOR_LINEAR_RANGE(2000000, 0, 10, 10000),
362 REGULATOR_LINEAR_RANGE(2100000, 0, 10, 10000),
377 if (ret != 0) { in mt6358_get_buck_voltage_sel()
396 if (ret != 0) { in mt6358_get_status()
436 if (ret != 0) { in mt6358_regulator_get_mode()
490 /* "Fixed" LDOs with output voltage calibration +0 ~ +10 mV */
506 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
508 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
510 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
512 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
514 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
516 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
518 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
520 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
522 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
523 MT6358_REG_FIXED("ldo_vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
524 MT6358_REG_FIXED("ldo_vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
525 MT6358_REG_FIXED("ldo_vcamio", VCAMIO, "vs1-ldo1", MT6358_LDO_VCAMIO_CON0, 0, 1800000),
526 MT6358_REG_FIXED("ldo_vcn18", VCN18, "vs1-ldo1", MT6358_LDO_VCN18_CON0, 0, 1800000),
527 MT6358_REG_FIXED("ldo_vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
528 MT6358_REG_FIXED("ldo_vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
529 MT6358_REG_FIXED("ldo_vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
530 MT6358_REG_FIXED("ldo_vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
531 MT6358_REG_FIXED("ldo_vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
532 MT6358_REG_FIXED("ldo_vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
533 MT6358_REG_FIXED("ldo_va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
534 MT6358_REG_FIXED("ldo_vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
535 MT6358_REG_FIXED("ldo_vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
537 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf),
539 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
541 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
543 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
545 MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00),
547 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
549 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
551 MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00),
553 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
555 MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
557 MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00),
559 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
561 MT6358_LDO_VLDO28_CON0_0, 0,
562 MT6358_VLDO28_ANA_CON0, 0x300),
564 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
566 MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
568 MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
570 MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
572 MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
578 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f, MT6358_VDRAM1_ANA_CON0, 8),
580 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 1),
582 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, MT6358_VPA_ANA_CON0, 3),
584 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 1),
586 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f, MT6358_VPROC_ANA_CON0, 2),
588 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, MT6358_VCORE_VGPU_ANA_CON0, 2),
590 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, MT6358_VS2_ANA_CON0, 8),
592 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f, MT6358_VMODEM_ANA_CON0, 8),
594 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, MT6358_VS1_ANA_CON0, 8),
595 MT6366_REG_FIXED("vrf12", VRF12, "vs2-ldo2", MT6358_LDO_VRF12_CON0, 0, 1200000),
596 MT6366_REG_FIXED("vio18", VIO18, "vs1-ldo1", MT6358_LDO_VIO18_CON0, 0, 1800000),
597 MT6366_REG_FIXED("vfe28", VFE28, "vsys-ldo1", MT6358_LDO_VFE28_CON0, 0, 2800000),
598 MT6366_REG_FIXED("vcn28", VCN28, "vsys-ldo1", MT6358_LDO_VCN28_CON0, 0, 2800000),
599 MT6366_REG_FIXED("vxo22", VXO22, "vsys-ldo1", MT6358_LDO_VXO22_CON0, 0, 2200000),
600 MT6366_REG_FIXED("vaux18", VAUX18, "vsys-ldo1", MT6358_LDO_VAUX18_CON0, 0, 1800000),
601 MT6366_REG_FIXED("vbif28", VBIF28, "vsys-ldo1", MT6358_LDO_VBIF28_CON0, 0, 2800000),
602 MT6366_REG_FIXED("vio28", VIO28, "vsys-ldo2", MT6358_LDO_VIO28_CON0, 0, 2800000),
603 MT6366_REG_FIXED("va12", VA12, "vs2-ldo2", MT6358_LDO_VA12_CON0, 0, 1200000),
604 MT6366_REG_FIXED("vrf18", VRF18, "vs1-ldo1", MT6358_LDO_VRF18_CON0, 0, 1800000),
605 MT6366_REG_FIXED("vaud28", VAUD28, "vsys-ldo1", MT6358_LDO_VAUD28_CON0, 0, 2800000),
607 MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0x10),
609 MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00),
611 MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00),
613 MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700),
615 MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00),
617 MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700),
619 MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700),
621 MT6358_LDO_VCN33_CON0_0, 0, MT6358_VCN33_ANA_CON0, 0x300),
623 MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00),
625 MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00),
627 MT6358_LDO_VCN18_CON0, 0, MT6358_VCN18_ANA_CON0, 0xf00),
629 MT6358_LDO_VM18_CON0, 0, MT6358_VM18_ANA_CON0, 0xf00),
631 MT6358_LDO_VMDDR_CON0, 0, MT6358_VMDDR_ANA_CON0, 0xf00),
633 MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON0, 0x7f),
635 MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON2, 0x7f),
637 MT6358_LDO_VSRAM_GPU_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON3, 0x7f),
639 MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON1, 0x7f),
641 MT6358_LDO_VSRAM_CORE_DBG0, 0x7f00, MT6358_LDO_VSRAM_CON5, 0x7f),
663 if (!(val & BIT(0))) in mt6358_sync_vcn33_setting()
664 return 0; in mt6358_sync_vcn33_setting()
667 ret = regmap_update_bits(mt6397->regmap, MT6358_LDO_VCN33_CON0_0, BIT(0), BIT(0)); in mt6358_sync_vcn33_setting()
674 ret = regmap_update_bits(mt6397->regmap, MT6358_LDO_VCN33_CON0_1, BIT(0), 0); in mt6358_sync_vcn33_setting()
680 return 0; in mt6358_sync_vcn33_setting()
709 for (i = 0; i < max_regulator; i++) { in mt6358_regulator_probe()
723 return 0; in mt6358_regulator_probe()
727 {"mt6358-regulator", 0},