Lines Matching full:vreg
47 #define MT6331_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ argument
49 [MT6331_ID_##vreg] = { \
51 .name = #vreg, \
55 .id = MT6331_ID_##vreg, \
72 #define MT6331_LDO_AO(match, vreg, ldo_volt_table, vosel, vosel_mask) \ argument
73 [MT6331_ID_##vreg] = { \
75 .name = #vreg, \
79 .id = MT6331_ID_##vreg, \
88 #define MT6331_LDO_S(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
91 [MT6331_ID_##vreg] = { \
93 .name = #vreg, \
97 .id = MT6331_ID_##vreg, \
112 #define MT6331_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
114 [MT6331_ID_##vreg] = { \
116 .name = #vreg, \
122 .id = MT6331_ID_##vreg, \
136 #define MT6331_REG_FIXED(match, vreg, enreg, enbit, qibit, volt, \ argument
138 [MT6331_ID_##vreg] = { \
140 .name = #vreg, \
146 .id = MT6331_ID_##vreg, \