Lines Matching full:vreg
39 #define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \ argument
41 [MT6323_ID_##vreg] = { \
43 .name = #vreg, \
47 .id = MT6323_ID_##vreg, \
63 #define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \ argument
65 [MT6323_ID_##vreg] = { \
67 .name = #vreg, \
71 .id = MT6323_ID_##vreg, \
85 #define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt, \ argument
87 [MT6323_ID_##vreg] = { \
89 .name = #vreg, \
93 .id = MT6323_ID_##vreg, \