Lines Matching +full:single +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * DA9121 Single-channel dual-phase 10A buck converter
4 * DA9130 Single-channel dual-phase 10A buck converter (Automotive)
5 * DA9217 Single-channel dual-phase 6A buck converter
6 * DA9122 Dual-channel single-phase 5A buck converter
7 * DA9131 Dual-channel single-phase 5A buck converter (Automotive)
8 * DA9220 Dual-channel single-phase 3A buck converter
9 * DA9132 Dual-channel single-phase 3A buck converter (Automotive)
23 #include <dt-bindings/regulator/dlg,da9121-regulator.h>
110 #define DA9xxx_MASK_SYS_STATUS_0_SG BIT(2)
111 #define DA9121_MASK_SYS_STATUS_0_TEMP_CRIT BIT(1)
112 #define DA9121_MASK_SYS_STATUS_0_TEMP_WARN BIT(0)
116 #define DA9xxx_MASK_SYS_STATUS_1_PG2 BIT(7)
117 #define DA9xxx_MASK_SYS_STATUS_1_OV2 BIT(6)
118 #define DA9xxx_MASK_SYS_STATUS_1_UV2 BIT(5)
119 #define DA9xxx_MASK_SYS_STATUS_1_OC2 BIT(4)
120 #define DA9121_MASK_SYS_STATUS_1_PG1 BIT(3)
121 #define DA9121_MASK_SYS_STATUS_1_OV1 BIT(2)
122 #define DA9121_MASK_SYS_STATUS_1_UV1 BIT(1)
123 #define DA9121_MASK_SYS_STATUS_1_OC1 BIT(0)
127 #define DA9121_MASK_SYS_STATUS_2_GPIO2 BIT(2)
128 #define DA9121_MASK_SYS_STATUS_2_GPIO1 BIT(1)
129 #define DA9121_MASK_SYS_STATUS_2_GPIO0 BIT(0)
133 #define DA9xxx_MASK_SYS_EVENT_0_E_SG BIT(2)
134 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_CRIT BIT(1)
135 #define DA9121_MASK_SYS_EVENT_0_E_TEMP_WARN BIT(0)
139 #define DA9xxx_MASK_SYS_EVENT_1_E_PG2 BIT(7)
140 #define DA9xxx_MASK_SYS_EVENT_1_E_OV2 BIT(6)
141 #define DA9xxx_MASK_SYS_EVENT_1_E_UV2 BIT(5)
142 #define DA9xxx_MASK_SYS_EVENT_1_E_OC2 BIT(4)
143 #define DA9121_MASK_SYS_EVENT_1_E_PG1 BIT(3)
144 #define DA9121_MASK_SYS_EVENT_1_E_OV1 BIT(2)
145 #define DA9121_MASK_SYS_EVENT_1_E_UV1 BIT(1)
146 #define DA9121_MASK_SYS_EVENT_1_E_OC1 BIT(0)
150 #define DA9121_MASK_SYS_EVENT_2_E_GPIO2 BIT(2)
151 #define DA9121_MASK_SYS_EVENT_2_E_GPIO1 BIT(1)
152 #define DA9121_MASK_SYS_EVENT_2_E_GPIO0 BIT(0)
156 #define DA9xxx_MASK_SYS_MASK_0_M_SG BIT(2)
157 #define DA9121_MASK_SYS_MASK_0_M_TEMP_CRIT BIT(1)
158 #define DA9121_MASK_SYS_MASK_0_M_TEMP_WARN BIT(0)
162 #define DA9xxx_MASK_SYS_MASK_1_M_PG2 BIT(7)
163 #define DA9xxx_MASK_SYS_MASK_1_M_OV2 BIT(6)
164 #define DA9xxx_MASK_SYS_MASK_1_M_UV2 BIT(5)
165 #define DA9xxx_MASK_SYS_MASK_1_M_OC2 BIT(4)
166 #define DA9121_MASK_SYS_MASK_1_M_PG1 BIT(3)
167 #define DA9121_MASK_SYS_MASK_1_M_OV1 BIT(2)
168 #define DA9121_MASK_SYS_MASK_1_M_UV1 BIT(1)
169 #define DA9121_MASK_SYS_MASK_1_M_OC1 BIT(0)
173 #define DA9121_MASK_SYS_MASK_2_M_GPIO2 BIT(2)
174 #define DA9121_MASK_SYS_MASK_2_M_GPIO1 BIT(1)
175 #define DA9121_MASK_SYS_MASK_2_M_GPIO0 BIT(0)
179 #define DA9121_MASK_SYS_MASK_3_M_VR_HOT BIT(3)
180 #define DA9xxx_MASK_SYS_MASK_3_M_SG_STAT BIT(2)
181 #define DA9xxx_MASK_SYS_MASK_3_M_PG2_STAT BIT(1)
182 #define DA9121_MASK_SYS_MASK_3_M_PG1_STAT BIT(0)
197 #define DA9121_MASK_SYS_CONFIG_2_OC_DVC_MASK BIT(4)
203 #define DA9121_MASK_SYS_CONFIG_3_I2C_TIMEOUT BIT(1)
208 #define DA9121_MASK_SYS_GPIO0_0_GPIO0_OBUF BIT(0)
212 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_FALL BIT(7)
213 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_DEB_RISE BIT(6)
215 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_PUPD BIT(3)
216 #define DA9121_MASK_SYS_GPIO0_1_GPIO0_POL BIT(2)
222 #define DA9121_MASK_SYS_GPIO1_0_GPIO1_OBUF BIT(0)
226 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_FALL BIT(7)
227 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_DEB_RISE BIT(6)
229 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_PUPD BIT(3)
230 #define DA9121_MASK_SYS_GPIO1_1_GPIO1_POL BIT(2)
236 #define DA9121_MASK_SYS_GPIO2_0_GPIO2_OBUF BIT(0)
240 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_FALL BIT(7)
241 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_DEB_RISE BIT(6)
243 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_PUPD BIT(3)
244 #define DA9121_MASK_SYS_GPIO2_1_GPIO2_POL BIT(2)
251 #define DA9121_MASK_BUCK_BUCKx_0_CHx_EN BIT(0)
257 #define DA9121_MASK_BUCK_BUCKx_1_CHx_PD_DIS BIT(0)
269 #define DA9121_MASK_BUCK_BUCKx_4_CHx_VSEL BIT(4)