amd/atl/reg_fields.h

71  *	D18F0x114 [DRAM Limit Address]
76  *	D18F7xE08 [DRAM Address Control]
79  *	D18F7x208 [DRAM Address Control]
132  * DRAM Address Range Valid
139  *	D18F0x110 [DRAM Base Address]
144  *	D18F7xE08 [DRAM Address Control]
147  *	D18F7x208 [DRAM Address Control]
153  * DRAM Base Address
160  *	D18F0x110 [DRAM Base Address]
165  *	D18F7xE00 [DRAM Base Address]
168  *	D18F7x200 [DRAM Base Address]
175  * DRAM Hole Base
182  *	D18F0x104 [DRAM Hole Control]
187  *	D18F7x104 [DRAM Hole Control]
194  * DRAM Limit Address
201  *	D18F0x114 [DRAM Limit Address]
206  *	D18F7xE04 [DRAM Limit Address]
209  *	D18F7x204 [DRAM Limit Address]
234  *	D18F7xE08 [DRAM Address Control]
239  *	D18F7x208 [DRAM Address Control]
263  *	D18F0x1B4 [DRAM Offset]
268  *	D18F7x140 [DRAM Offset]
287  *	D18F0x1B4 [DRAM Offset]
292  *	D18F7x140 [DRAM Offset]
306  *	D18F0x110 [DRAM Base Address]
311  *	D18F7xE0C [DRAM Address Interleave]
314  *	D18F7x20C [DRAM Address Interleave]
329  *	D18F0x110 [DRAM Base Address]
334  *	D18F7xE0C [DRAM Address Interleave]
337  *	D18F7x20C [DRAM Address Interleave]
354  *	D18F0x114 [DRAM Limit Address]
357  *	D18F0x110 [DRAM Base Address]
361  *	D18F7xE0C [DRAM Address Interleave]
364  *	D18F7x20C [DRAM Address Interleave]
380  *	D18F0x114 [DRAM Limit Address]
383  *	D18F0x110 [DRAM Base Address]
387  *	D18F7xE0C [DRAM Address Interleave]
390  *	D18F7x20C [DRAM Address Interleave]
404  *	D18F0x110 [DRAM Base Address]
409  *	D18F7xE08 [DRAM Address Control]
412  *	D18F7x208 [DRAM Address Control]
427  *	D18F2x90 [Non-power-of-2 channel Configuration Register for COH_ST DRAM Address Maps]
529  *	D18F7xE08 [DRAM Address Control]
532  *	D18F7x208 [DRAM Address Control]
549  *	D18F7xE08 [DRAM Address Control]
552  *	D18F7x208 [DRAM Address Control]