Lines Matching +full:max +full:- +full:outbound +full:- +full:regions
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RapidIO mport driver for Tsi721 PCIExpress-to-SRIO bridge
19 #include <linux/dma-mapping.h>
32 static int pcie_mrrs = -1;
47 * tsi721_lcread - read from local SREP config space
56 * Returns: %0 on success or %-EINVAL on failure.
61 struct tsi721_device *priv = mport->priv; in tsi721_lcread()
64 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcread()
66 *data = ioread32(priv->regs + offset); in tsi721_lcread()
72 * tsi721_lcwrite - write into local SREP config space
81 * Returns: %0 on success or %-EINVAL on failure.
86 struct tsi721_device *priv = mport->priv; in tsi721_lcwrite()
89 return -EINVAL; /* only 32-bit access is supported */ in tsi721_lcwrite()
91 iowrite32(data, priv->regs + offset); in tsi721_lcwrite()
97 * tsi721_maint_dma - Helper function to generate RapidIO maintenance
109 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure.
115 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(priv->mdma.ch_id); in tsi721_maint_dma()
122 if (offset > (RIO_MAINT_SPACE_SZ - len) || (len != sizeof(u32))) in tsi721_maint_dma()
123 return -EINVAL; in tsi721_maint_dma()
127 bd_ptr = priv->mdma.bd_base; in tsi721_maint_dma()
153 tsi_debug(MAINT, &priv->pdev->dev, in tsi721_maint_dma()
155 priv->mdma.ch_id, ch_stat); in tsi721_maint_dma()
158 err = -EIO; in tsi721_maint_dma()
167 tsi_debug(MAINT, &priv->pdev->dev, "DMA ABORT ch_stat=%x", in tsi721_maint_dma()
169 tsi_debug(MAINT, &priv->pdev->dev, in tsi721_maint_dma()
180 err = -EIO; in tsi721_maint_dma()
202 * tsi721_cread_dma - Generate a RapidIO maintenance read transaction
213 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure.
218 struct tsi721_device *priv = mport->priv; in tsi721_cread_dma()
220 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, in tsi721_cread_dma()
225 * tsi721_cwrite_dma - Generate a RapidIO maintenance write transaction
236 * Returns: %0 on success and %-EINVAL or %-EFAULT on failure.
241 struct tsi721_device *priv = mport->priv; in tsi721_cwrite_dma()
244 return tsi721_maint_dma(priv, mport->sys_size, destid, hopcount, in tsi721_cwrite_dma()
249 * tsi721_pw_handler - Tsi721 inbound port-write interrupt handler
252 * Handles inbound port-write interrupts. Copies PW message from an internal
265 pw_stat = ioread32(priv->regs + TSI721_RIO_PW_RX_STAT); in tsi721_pw_handler()
268 pw_buf[0] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(0)); in tsi721_pw_handler()
269 pw_buf[1] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(1)); in tsi721_pw_handler()
270 pw_buf[2] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(2)); in tsi721_pw_handler()
271 pw_buf[3] = ioread32(priv->regs + TSI721_RIO_PW_RX_CAPT(3)); in tsi721_pw_handler()
276 spin_lock(&priv->pw_fifo_lock); in tsi721_pw_handler()
277 if (kfifo_avail(&priv->pw_fifo) >= TSI721_RIO_PW_MSG_SIZE) in tsi721_pw_handler()
278 kfifo_in(&priv->pw_fifo, pw_buf, in tsi721_pw_handler()
281 priv->pw_discard_count++; in tsi721_pw_handler()
282 spin_unlock(&priv->pw_fifo_lock); in tsi721_pw_handler()
287 priv->regs + TSI721_RIO_PW_RX_STAT); in tsi721_pw_handler()
289 schedule_work(&priv->pw_work); in tsi721_pw_handler()
301 * Process port-write messages in tsi721_pw_dpc()
303 while (kfifo_out_spinlocked(&priv->pw_fifo, (unsigned char *)&pwmsg, in tsi721_pw_dpc()
304 TSI721_RIO_PW_MSG_SIZE, &priv->pw_fifo_lock)) { in tsi721_pw_dpc()
305 /* Pass the port-write message to RIO core for processing */ in tsi721_pw_dpc()
306 rio_inb_pwrite_handler(&priv->mport, &pwmsg); in tsi721_pw_dpc()
311 * tsi721_pw_enable - enable/disable port-write interface init
313 * @enable: 1=enable; 0=disable port-write message handling
319 struct tsi721_device *priv = mport->priv; in tsi721_pw_enable()
322 rval = ioread32(priv->regs + TSI721_RIO_EM_INT_ENABLE); in tsi721_pw_enable()
331 priv->regs + TSI721_RIO_PW_RX_STAT); in tsi721_pw_enable()
333 iowrite32(rval, priv->regs + TSI721_RIO_EM_INT_ENABLE); in tsi721_pw_enable()
339 * tsi721_dsend - Send a RapidIO doorbell
343 * @data: 16-bit info field of RapidIO doorbell
352 struct tsi721_device *priv = mport->priv; in tsi721_dsend()
355 offset = (((mport->sys_size) ? RIO_TT_CODE_16 : RIO_TT_CODE_8) << 18) | in tsi721_dsend()
358 tsi_debug(DBELL, &priv->pdev->dev, in tsi721_dsend()
360 iowrite16be(data, priv->odb_base + offset); in tsi721_dsend()
366 * tsi721_dbell_handler - Tsi721 doorbell interrupt handler
367 * @priv: tsi721 device-specific data structure
381 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); in tsi721_dbell_handler()
384 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); in tsi721_dbell_handler()
386 schedule_work(&priv->idb_work); in tsi721_dbell_handler()
409 mport = &priv->mport; in tsi721_db_dpc()
411 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; in tsi721_db_dpc()
412 rd_ptr = ioread32(priv->regs + TSI721_IDQ_RP(IDB_QUEUE)) % IDB_QSIZE; in tsi721_db_dpc()
415 idb_entry = (u64 *)(priv->idb_base + in tsi721_db_dpc()
423 list_for_each_entry(dbell, &mport->dbells, node) { in tsi721_db_dpc()
424 if ((dbell->res->start <= DBELL_INF(idb.bytes)) && in tsi721_db_dpc()
425 (dbell->res->end >= DBELL_INF(idb.bytes))) { in tsi721_db_dpc()
432 dbell->dinb(mport, dbell->dev_id, DBELL_SID(idb.bytes), in tsi721_db_dpc()
435 tsi_debug(DBELL, &priv->pdev->dev, in tsi721_db_dpc()
441 wr_ptr = ioread32(priv->regs + in tsi721_db_dpc()
445 iowrite32(rd_ptr & (IDB_QSIZE - 1), in tsi721_db_dpc()
446 priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); in tsi721_db_dpc()
448 /* Re-enable IDB interrupts */ in tsi721_db_dpc()
449 regval = ioread32(priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); in tsi721_db_dpc()
452 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); in tsi721_db_dpc()
454 wr_ptr = ioread32(priv->regs + TSI721_IDQ_WP(IDB_QUEUE)) % IDB_QSIZE; in tsi721_db_dpc()
456 schedule_work(&priv->idb_work); in tsi721_db_dpc()
460 * tsi721_irqhandler - Tsi721 interrupt handler
462 * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
465 * interrupt events and calls an event-specific handler(s).
477 /* For MSI mode disable all device-level interrupts */ in tsi721_irqhandler()
478 if (priv->flags & TSI721_USING_MSI) in tsi721_irqhandler()
479 iowrite32(0, priv->regs + TSI721_DEV_INTE); in tsi721_irqhandler()
481 dev_int = ioread32(priv->regs + TSI721_DEV_INT); in tsi721_irqhandler()
485 dev_ch_int = ioread32(priv->regs + TSI721_DEV_CHAN_INT); in tsi721_irqhandler()
491 intval = ioread32(priv->regs + in tsi721_irqhandler()
496 tsi_info(&priv->pdev->dev, in tsi721_irqhandler()
501 priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_irqhandler()
502 ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_irqhandler()
515 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_irqhandler()
517 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_irqhandler()
529 if (dev_ch_int & TSI721_INT_OMSG_CHAN_M) { /* Outbound Msg */ in tsi721_irqhandler()
531 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_irqhandler()
533 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_irqhandler()
536 * Process Outbound Message interrupts for each MBOX in tsi721_irqhandler()
549 intval = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); in tsi721_irqhandler()
559 tsi_debug(DMA, &priv->pdev->dev, in tsi721_irqhandler()
565 tsi721_bdma_handler(&priv->bdma[ch]); in tsi721_irqhandler()
571 /* For MSI mode re-enable device-level interrupts */ in tsi721_irqhandler()
572 if (priv->flags & TSI721_USING_MSI) { in tsi721_irqhandler()
575 iowrite32(dev_int, priv->regs + TSI721_DEV_INTE); in tsi721_irqhandler()
587 priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_interrupts_init()
589 priv->regs + TSI721_SR_CHINTE(IDB_QUEUE)); in tsi721_interrupts_init()
593 priv->regs + TSI721_RIO_EM_DEV_INT_EN); in tsi721_interrupts_init()
603 iowrite32(intr, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_interrupts_init()
605 if (priv->flags & TSI721_USING_MSIX) in tsi721_interrupts_init()
611 iowrite32(intr, priv->regs + TSI721_DEV_INTE); in tsi721_interrupts_init()
612 ioread32(priv->regs + TSI721_DEV_INTE); in tsi721_interrupts_init()
617 * tsi721_omsg_msix - MSI-X interrupt handler for outbound messaging
619 * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
621 * Handles outbound messaging interrupts signaled using MSI-X.
630 mbox = (irq - priv->msix[TSI721_VECT_OMB0_DONE].vector) % RIO_MAX_MBOX; in tsi721_omsg_msix()
636 * tsi721_imsg_msix - MSI-X interrupt handler for inbound messaging
638 * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
640 * Handles inbound messaging interrupts signaled using MSI-X.
649 mbox = (irq - priv->msix[TSI721_VECT_IMB0_RCV].vector) % RIO_MAX_MBOX; in tsi721_imsg_msix()
655 * tsi721_srio_msix - Tsi721 MSI-X SRIO MAC interrupt handler
657 * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
669 srio_int = ioread32(priv->regs + TSI721_RIO_EM_INT_STAT); in tsi721_srio_msix()
677 * tsi721_sr2pc_ch_msix - Tsi721 MSI-X SR2PC Channel interrupt handler
679 * @ptr: Pointer to interrupt-specific data (tsi721_device structure)
693 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_sr2pc_ch_msix()
698 iowrite32(sr_ch_int, priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_sr2pc_ch_msix()
700 sr_ch_int = ioread32(priv->regs + TSI721_SR_CHINT(IDB_QUEUE)); in tsi721_sr2pc_ch_msix()
706 * tsi721_request_msix - register interrupt service for MSI-X mode.
707 * @priv: tsi721 device-specific data structure
709 * Registers MSI-X interrupt service routines for interrupts that are active
713 * Returns: %0 on success or -errno value on failure.
719 err = request_irq(priv->msix[TSI721_VECT_IDB].vector, in tsi721_request_msix()
721 priv->msix[TSI721_VECT_IDB].irq_name, (void *)priv); in tsi721_request_msix()
725 err = request_irq(priv->msix[TSI721_VECT_PWRX].vector, in tsi721_request_msix()
727 priv->msix[TSI721_VECT_PWRX].irq_name, (void *)priv); in tsi721_request_msix()
729 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); in tsi721_request_msix()
737 * tsi721_enable_msix - Attempts to enable MSI-X support for Tsi721.
740 * Configures MSI-X support for Tsi721. Supports only an exact number
743 * Returns: %0 on success or -errno value on failure.
755 * Initialize MSI-X entries for Messaging Engine: in tsi721_enable_msix()
756 * this driver supports four RIO mailboxes (inbound and outbound) in tsi721_enable_msix()
773 * Initialize MSI-X entries for Block DMA Engine: in tsi721_enable_msix()
785 err = pci_enable_msix_exact(priv->pdev, entries, ARRAY_SIZE(entries)); in tsi721_enable_msix()
787 tsi_err(&priv->pdev->dev, in tsi721_enable_msix()
788 "Failed to enable MSI-X (err=%d)", err); in tsi721_enable_msix()
793 * Copy MSI-X vector information into tsi721 private structure in tsi721_enable_msix()
795 priv->msix[TSI721_VECT_IDB].vector = entries[TSI721_VECT_IDB].vector; in tsi721_enable_msix()
796 snprintf(priv->msix[TSI721_VECT_IDB].irq_name, IRQ_DEVICE_NAME_MAX, in tsi721_enable_msix()
797 DRV_NAME "-idb@pci:%s", pci_name(priv->pdev)); in tsi721_enable_msix()
798 priv->msix[TSI721_VECT_PWRX].vector = entries[TSI721_VECT_PWRX].vector; in tsi721_enable_msix()
799 snprintf(priv->msix[TSI721_VECT_PWRX].irq_name, IRQ_DEVICE_NAME_MAX, in tsi721_enable_msix()
800 DRV_NAME "-pwrx@pci:%s", pci_name(priv->pdev)); in tsi721_enable_msix()
803 priv->msix[TSI721_VECT_IMB0_RCV + i].vector = in tsi721_enable_msix()
805 snprintf(priv->msix[TSI721_VECT_IMB0_RCV + i].irq_name, in tsi721_enable_msix()
806 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbr%d@pci:%s", in tsi721_enable_msix()
807 i, pci_name(priv->pdev)); in tsi721_enable_msix()
809 priv->msix[TSI721_VECT_IMB0_INT + i].vector = in tsi721_enable_msix()
811 snprintf(priv->msix[TSI721_VECT_IMB0_INT + i].irq_name, in tsi721_enable_msix()
812 IRQ_DEVICE_NAME_MAX, DRV_NAME "-imbi%d@pci:%s", in tsi721_enable_msix()
813 i, pci_name(priv->pdev)); in tsi721_enable_msix()
815 priv->msix[TSI721_VECT_OMB0_DONE + i].vector = in tsi721_enable_msix()
817 snprintf(priv->msix[TSI721_VECT_OMB0_DONE + i].irq_name, in tsi721_enable_msix()
818 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombd%d@pci:%s", in tsi721_enable_msix()
819 i, pci_name(priv->pdev)); in tsi721_enable_msix()
821 priv->msix[TSI721_VECT_OMB0_INT + i].vector = in tsi721_enable_msix()
823 snprintf(priv->msix[TSI721_VECT_OMB0_INT + i].irq_name, in tsi721_enable_msix()
824 IRQ_DEVICE_NAME_MAX, DRV_NAME "-ombi%d@pci:%s", in tsi721_enable_msix()
825 i, pci_name(priv->pdev)); in tsi721_enable_msix()
830 priv->msix[TSI721_VECT_DMA0_DONE + i].vector = in tsi721_enable_msix()
832 snprintf(priv->msix[TSI721_VECT_DMA0_DONE + i].irq_name, in tsi721_enable_msix()
833 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmad%d@pci:%s", in tsi721_enable_msix()
834 i, pci_name(priv->pdev)); in tsi721_enable_msix()
836 priv->msix[TSI721_VECT_DMA0_INT + i].vector = in tsi721_enable_msix()
838 snprintf(priv->msix[TSI721_VECT_DMA0_INT + i].irq_name, in tsi721_enable_msix()
839 IRQ_DEVICE_NAME_MAX, DRV_NAME "-dmai%d@pci:%s", in tsi721_enable_msix()
840 i, pci_name(priv->pdev)); in tsi721_enable_msix()
853 if (priv->flags & TSI721_USING_MSIX) in tsi721_request_irq()
857 err = request_irq(priv->pdev->irq, tsi721_irqhandler, in tsi721_request_irq()
858 (priv->flags & TSI721_USING_MSI) ? 0 : IRQF_SHARED, in tsi721_request_irq()
862 tsi_err(&priv->pdev->dev, in tsi721_request_irq()
871 if (priv->flags & TSI721_USING_MSIX) { in tsi721_free_irq()
872 free_irq(priv->msix[TSI721_VECT_IDB].vector, (void *)priv); in tsi721_free_irq()
873 free_irq(priv->msix[TSI721_VECT_PWRX].vector, (void *)priv); in tsi721_free_irq()
876 free_irq(priv->pdev->irq, (void *)priv); in tsi721_free_irq()
889 int new_win_idx = -1; in tsi721_obw_alloc()
892 bar_base = pbar->base; in tsi721_obw_alloc()
893 bar_end = bar_base + pbar->size; in tsi721_obw_alloc()
899 if (!priv->ob_win[i].active) { in tsi721_obw_alloc()
901 new_win = &priv->ob_win[i]; in tsi721_obw_alloc()
911 win = &priv->ob_win[i]; in tsi721_obw_alloc()
913 if (win->base >= bar_base && win->base < bar_end) { in tsi721_obw_alloc()
914 if (win_base < (win->base + win->size) && in tsi721_obw_alloc()
915 (win_base + size) > win->base) { in tsi721_obw_alloc()
917 win_base = win->base + win->size; in tsi721_obw_alloc()
926 return -ENOMEM; in tsi721_obw_alloc()
929 tsi_err(&priv->pdev->dev, "OBW count tracking failed"); in tsi721_obw_alloc()
930 return -EIO; in tsi721_obw_alloc()
933 new_win->active = true; in tsi721_obw_alloc()
934 new_win->base = win_base; in tsi721_obw_alloc()
935 new_win->size = size; in tsi721_obw_alloc()
936 new_win->pbar = pbar; in tsi721_obw_alloc()
937 priv->obwin_cnt--; in tsi721_obw_alloc()
938 pbar->free -= size; in tsi721_obw_alloc()
946 struct tsi721_device *priv = mport->priv; in tsi721_map_outb_win()
950 int obw = -1; in tsi721_map_outb_win()
954 int ret = -ENOMEM; in tsi721_map_outb_win()
956 tsi_debug(OBW, &priv->pdev->dev, in tsi721_map_outb_win()
959 if (!is_power_of_2(size) || (size < 0x8000) || (rstart & (size - 1))) in tsi721_map_outb_win()
960 return -EINVAL; in tsi721_map_outb_win()
962 if (priv->obwin_cnt == 0) in tsi721_map_outb_win()
963 return -EBUSY; in tsi721_map_outb_win()
966 if (priv->p2r_bar[i].free >= size) { in tsi721_map_outb_win()
967 pbar = &priv->p2r_bar[i]; in tsi721_map_outb_win()
977 WARN_ON(obw == -1); in tsi721_map_outb_win()
978 ob_win = &priv->ob_win[obw]; in tsi721_map_outb_win()
979 ob_win->destid = destid; in tsi721_map_outb_win()
980 ob_win->rstart = rstart; in tsi721_map_outb_win()
981 tsi_debug(OBW, &priv->pdev->dev, in tsi721_map_outb_win()
982 "allocated OBW%d @%llx", obw, ob_win->base); in tsi721_map_outb_win()
985 * Configure Outbound Window in tsi721_map_outb_win()
997 while (ioread32(priv->regs + TSI721_ZONE_SEL) & in tsi721_map_outb_win()
1004 iowrite32(rval, priv->regs + TSI721_LUT_DATA0); in tsi721_map_outb_win()
1006 iowrite32(rval, priv->regs + TSI721_LUT_DATA1); in tsi721_map_outb_win()
1008 iowrite32(rval, priv->regs + TSI721_LUT_DATA2); in tsi721_map_outb_win()
1011 iowrite32(rval, priv->regs + TSI721_ZONE_SEL); in tsi721_map_outb_win()
1017 priv->regs + TSI721_OBWINSZ(obw)); in tsi721_map_outb_win()
1018 iowrite32((u32)(ob_win->base >> 32), priv->regs + TSI721_OBWINUB(obw)); in tsi721_map_outb_win()
1019 iowrite32((u32)(ob_win->base & TSI721_OBWINLB_BA) | TSI721_OBWINLB_WEN, in tsi721_map_outb_win()
1020 priv->regs + TSI721_OBWINLB(obw)); in tsi721_map_outb_win()
1022 *laddr = ob_win->base; in tsi721_map_outb_win()
1029 struct tsi721_device *priv = mport->priv; in tsi721_unmap_outb_win()
1033 tsi_debug(OBW, &priv->pdev->dev, "did=%d ra=0x%llx", destid, rstart); in tsi721_unmap_outb_win()
1036 ob_win = &priv->ob_win[i]; in tsi721_unmap_outb_win()
1038 if (ob_win->active && in tsi721_unmap_outb_win()
1039 ob_win->destid == destid && ob_win->rstart == rstart) { in tsi721_unmap_outb_win()
1040 tsi_debug(OBW, &priv->pdev->dev, in tsi721_unmap_outb_win()
1041 "free OBW%d @%llx", i, ob_win->base); in tsi721_unmap_outb_win()
1042 ob_win->active = false; in tsi721_unmap_outb_win()
1043 iowrite32(0, priv->regs + TSI721_OBWINLB(i)); in tsi721_unmap_outb_win()
1044 ob_win->pbar->free += ob_win->size; in tsi721_unmap_outb_win()
1045 priv->obwin_cnt++; in tsi721_unmap_outb_win()
1052 * tsi721_init_pc2sr_mapping - initializes outbound (PCIe->SRIO)
1053 * translation regions.
1056 * Disables SREP translation regions.
1065 iowrite32(0, priv->regs + TSI721_OBWINLB(i)); in tsi721_init_pc2sr_mapping()
1068 iowrite32(0, priv->regs + TSI721_LUT_DATA0); in tsi721_init_pc2sr_mapping()
1069 iowrite32(0, priv->regs + TSI721_LUT_DATA1); in tsi721_init_pc2sr_mapping()
1070 iowrite32(0, priv->regs + TSI721_LUT_DATA2); in tsi721_init_pc2sr_mapping()
1074 while (ioread32(priv->regs + TSI721_ZONE_SEL) & in tsi721_init_pc2sr_mapping()
1079 iowrite32(rval, priv->regs + TSI721_ZONE_SEL); in tsi721_init_pc2sr_mapping()
1083 if (priv->p2r_bar[0].size == 0 && priv->p2r_bar[1].size == 0) { in tsi721_init_pc2sr_mapping()
1084 priv->obwin_cnt = 0; in tsi721_init_pc2sr_mapping()
1088 priv->p2r_bar[0].free = priv->p2r_bar[0].size; in tsi721_init_pc2sr_mapping()
1089 priv->p2r_bar[1].free = priv->p2r_bar[1].size; in tsi721_init_pc2sr_mapping()
1092 priv->ob_win[i].active = false; in tsi721_init_pc2sr_mapping()
1094 priv->obwin_cnt = TSI721_OBWIN_NUM; in tsi721_init_pc2sr_mapping()
1098 * tsi721_rio_map_inb_mem -- Mapping inbound memory region.
1105 * Return: 0 -- Success.
1113 struct tsi721_device *priv = mport->priv; in tsi721_rio_map_inb_mem()
1114 int i, avail = -1; in tsi721_rio_map_inb_mem()
1122 int ret = -EBUSY; in tsi721_rio_map_inb_mem()
1124 /* Max IBW size supported by HW is 16GB */ in tsi721_rio_map_inb_mem()
1126 return -EINVAL; in tsi721_rio_map_inb_mem()
1132 ibw_start = lstart & ~(ibw_size - 1); in tsi721_rio_map_inb_mem()
1134 tsi_debug(IBW, &priv->pdev->dev, in tsi721_rio_map_inb_mem()
1135 "Direct (RIO_0x%llx -> PCIe_%pad), size=0x%llx, ibw_start = 0x%llx", in tsi721_rio_map_inb_mem()
1140 ibw_start = lstart & ~(ibw_size - 1); in tsi721_rio_map_inb_mem()
1141 /* Check for crossing IBW max size 16GB */ in tsi721_rio_map_inb_mem()
1143 return -EBUSY; in tsi721_rio_map_inb_mem()
1150 return -ENOMEM; in tsi721_rio_map_inb_mem()
1153 tsi_debug(IBW, &priv->pdev->dev, in tsi721_rio_map_inb_mem()
1154 "Translated (RIO_0x%llx -> PCIe_%pad), size=0x%llx", in tsi721_rio_map_inb_mem()
1158 ((u64)lstart & (size - 1)) || (rstart & (size - 1))) in tsi721_rio_map_inb_mem()
1159 return -EINVAL; in tsi721_rio_map_inb_mem()
1160 if (priv->ibwin_cnt == 0) in tsi721_rio_map_inb_mem()
1161 return -EBUSY; in tsi721_rio_map_inb_mem()
1168 * Scan for overlapping with active regions and mark the first available in tsi721_rio_map_inb_mem()
1172 ib_win = &priv->ib_win[i]; in tsi721_rio_map_inb_mem()
1174 if (!ib_win->active) { in tsi721_rio_map_inb_mem()
1175 if (avail == -1) { in tsi721_rio_map_inb_mem()
1179 } else if (ibw_start < (ib_win->rstart + ib_win->size) && in tsi721_rio_map_inb_mem()
1180 (ibw_start + ibw_size) > ib_win->rstart) { in tsi721_rio_map_inb_mem()
1182 if (!direct || ib_win->xlat) { in tsi721_rio_map_inb_mem()
1183 ret = -EFAULT; in tsi721_rio_map_inb_mem()
1189 * requested fragments - check if this new request fits in tsi721_rio_map_inb_mem()
1192 if (rstart >= ib_win->rstart && in tsi721_rio_map_inb_mem()
1193 (rstart + size) <= (ib_win->rstart + in tsi721_rio_map_inb_mem()
1194 ib_win->size)) { in tsi721_rio_map_inb_mem()
1195 /* We are in - no further mapping required */ in tsi721_rio_map_inb_mem()
1196 map->lstart = lstart; in tsi721_rio_map_inb_mem()
1197 list_add_tail(&map->node, &ib_win->mappings); in tsi721_rio_map_inb_mem()
1201 ret = -EFAULT; in tsi721_rio_map_inb_mem()
1211 regval = ioread32(priv->regs + TSI721_IBWIN_LB(i)); in tsi721_rio_map_inb_mem()
1213 ret = -EIO; in tsi721_rio_map_inb_mem()
1217 ib_win = &priv->ib_win[i]; in tsi721_rio_map_inb_mem()
1218 ib_win->active = true; in tsi721_rio_map_inb_mem()
1219 ib_win->rstart = ibw_start; in tsi721_rio_map_inb_mem()
1220 ib_win->lstart = loc_start; in tsi721_rio_map_inb_mem()
1221 ib_win->size = ibw_size; in tsi721_rio_map_inb_mem()
1222 ib_win->xlat = (lstart != rstart); in tsi721_rio_map_inb_mem()
1223 INIT_LIST_HEAD(&ib_win->mappings); in tsi721_rio_map_inb_mem()
1231 map->lstart = lstart; in tsi721_rio_map_inb_mem()
1232 list_add_tail(&map->node, &ib_win->mappings); in tsi721_rio_map_inb_mem()
1236 priv->regs + TSI721_IBWIN_SZ(i)); in tsi721_rio_map_inb_mem()
1238 iowrite32(((u64)loc_start >> 32), priv->regs + TSI721_IBWIN_TUA(i)); in tsi721_rio_map_inb_mem()
1240 priv->regs + TSI721_IBWIN_TLA(i)); in tsi721_rio_map_inb_mem()
1242 iowrite32(ibw_start >> 32, priv->regs + TSI721_IBWIN_UB(i)); in tsi721_rio_map_inb_mem()
1244 priv->regs + TSI721_IBWIN_LB(i)); in tsi721_rio_map_inb_mem()
1246 priv->ibwin_cnt--; in tsi721_rio_map_inb_mem()
1248 tsi_debug(IBW, &priv->pdev->dev, in tsi721_rio_map_inb_mem()
1249 "Configured IBWIN%d (RIO_0x%llx -> PCIe_%pad), size=0x%llx", in tsi721_rio_map_inb_mem()
1259 * tsi721_rio_unmap_inb_mem -- Unmapping inbound memory region.
1266 struct tsi721_device *priv = mport->priv; in tsi721_rio_unmap_inb_mem()
1270 tsi_debug(IBW, &priv->pdev->dev, in tsi721_rio_unmap_inb_mem()
1275 ib_win = &priv->ib_win[i]; in tsi721_rio_unmap_inb_mem()
1278 if (!ib_win->active || in tsi721_rio_unmap_inb_mem()
1279 (ib_win->xlat && lstart != ib_win->lstart)) in tsi721_rio_unmap_inb_mem()
1282 if (lstart >= ib_win->lstart && in tsi721_rio_unmap_inb_mem()
1283 lstart < (ib_win->lstart + ib_win->size)) { in tsi721_rio_unmap_inb_mem()
1285 if (!ib_win->xlat) { in tsi721_rio_unmap_inb_mem()
1290 &ib_win->mappings, node) { in tsi721_rio_unmap_inb_mem()
1291 if (map->lstart == lstart) { in tsi721_rio_unmap_inb_mem()
1292 list_del(&map->node); in tsi721_rio_unmap_inb_mem()
1302 if (!list_empty(&ib_win->mappings)) in tsi721_rio_unmap_inb_mem()
1306 tsi_debug(IBW, &priv->pdev->dev, "Disable IBWIN_%d", i); in tsi721_rio_unmap_inb_mem()
1307 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); in tsi721_rio_unmap_inb_mem()
1308 ib_win->active = false; in tsi721_rio_unmap_inb_mem()
1309 priv->ibwin_cnt++; in tsi721_rio_unmap_inb_mem()
1315 tsi_debug(IBW, &priv->pdev->dev, in tsi721_rio_unmap_inb_mem()
1320 * tsi721_init_sr2pc_mapping - initializes inbound (SRIO->PCIe)
1321 * translation regions.
1332 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); in tsi721_init_sr2pc_mapping()
1333 priv->ibwin_cnt = TSI721_IBWIN_NUM; in tsi721_init_sr2pc_mapping()
1337 * tsi721_close_sr2pc_mapping - closes all active inbound (SRIO->PCIe)
1338 * translation regions.
1348 ib_win = &priv->ib_win[i]; in tsi721_close_sr2pc_mapping()
1349 if (ib_win->active) { in tsi721_close_sr2pc_mapping()
1350 iowrite32(0, priv->regs + TSI721_IBWIN_LB(i)); in tsi721_close_sr2pc_mapping()
1351 ib_win->active = false; in tsi721_close_sr2pc_mapping()
1357 * tsi721_port_write_init - Inbound port write interface init
1361 * Returns: %0 on success or %-ENOMEM on failure.
1365 priv->pw_discard_count = 0; in tsi721_port_write_init()
1366 INIT_WORK(&priv->pw_work, tsi721_pw_dpc); in tsi721_port_write_init()
1367 spin_lock_init(&priv->pw_fifo_lock); in tsi721_port_write_init()
1368 if (kfifo_alloc(&priv->pw_fifo, in tsi721_port_write_init()
1370 tsi_err(&priv->pdev->dev, "PW FIFO allocation failed"); in tsi721_port_write_init()
1371 return -ENOMEM; in tsi721_port_write_init()
1374 /* Use reliable port-write capture mode */ in tsi721_port_write_init()
1375 iowrite32(TSI721_RIO_PW_CTL_PWC_REL, priv->regs + TSI721_RIO_PW_CTL); in tsi721_port_write_init()
1381 kfifo_free(&priv->pw_fifo); in tsi721_port_write_free()
1386 /* Outbound Doorbells do not require any setup. in tsi721_doorbell_init()
1392 priv->db_discard_count = 0; in tsi721_doorbell_init()
1393 INIT_WORK(&priv->idb_work, tsi721_db_dpc); in tsi721_doorbell_init()
1396 priv->idb_base = dma_alloc_coherent(&priv->pdev->dev, in tsi721_doorbell_init()
1398 &priv->idb_dma, GFP_KERNEL); in tsi721_doorbell_init()
1399 if (!priv->idb_base) in tsi721_doorbell_init()
1400 return -ENOMEM; in tsi721_doorbell_init()
1402 tsi_debug(DBELL, &priv->pdev->dev, in tsi721_doorbell_init()
1404 priv->idb_base, &priv->idb_dma); in tsi721_doorbell_init()
1407 priv->regs + TSI721_IDQ_SIZE(IDB_QUEUE)); in tsi721_doorbell_init()
1408 iowrite32(((u64)priv->idb_dma >> 32), in tsi721_doorbell_init()
1409 priv->regs + TSI721_IDQ_BASEU(IDB_QUEUE)); in tsi721_doorbell_init()
1410 iowrite32(((u64)priv->idb_dma & TSI721_IDQ_BASEL_ADDR), in tsi721_doorbell_init()
1411 priv->regs + TSI721_IDQ_BASEL(IDB_QUEUE)); in tsi721_doorbell_init()
1413 iowrite32(0, priv->regs + TSI721_IDQ_MASK(IDB_QUEUE)); in tsi721_doorbell_init()
1415 iowrite32(TSI721_IDQ_INIT, priv->regs + TSI721_IDQ_CTL(IDB_QUEUE)); in tsi721_doorbell_init()
1417 iowrite32(0, priv->regs + TSI721_IDQ_RP(IDB_QUEUE)); in tsi721_doorbell_init()
1424 if (priv->idb_base == NULL) in tsi721_doorbell_free()
1428 dma_free_coherent(&priv->pdev->dev, IDB_QSIZE * TSI721_IDB_ENTRY_SIZE, in tsi721_doorbell_free()
1429 priv->idb_base, priv->idb_dma); in tsi721_doorbell_free()
1430 priv->idb_base = NULL; in tsi721_doorbell_free()
1434 * tsi721_bdma_maint_init - Initialize maintenance request BDMA channel.
1440 * Returns: %0 on success or %-ENOMEM on failure.
1451 tsi_debug(MAINT, &priv->pdev->dev, in tsi721_bdma_maint_init()
1458 priv->mdma.ch_id = TSI721_DMACH_MAINT; in tsi721_bdma_maint_init()
1459 regs = priv->regs + TSI721_DMAC_BASE(TSI721_DMACH_MAINT); in tsi721_bdma_maint_init()
1462 bd_ptr = dma_alloc_coherent(&priv->pdev->dev, in tsi721_bdma_maint_init()
1466 return -ENOMEM; in tsi721_bdma_maint_init()
1468 priv->mdma.bd_num = bd_num; in tsi721_bdma_maint_init()
1469 priv->mdma.bd_phys = bd_phys; in tsi721_bdma_maint_init()
1470 priv->mdma.bd_base = bd_ptr; in tsi721_bdma_maint_init()
1472 tsi_debug(MAINT, &priv->pdev->dev, "DMA descriptors @ %p (phys = %pad)", in tsi721_bdma_maint_init()
1479 sts_ptr = dma_alloc_coherent(&priv->pdev->dev, in tsi721_bdma_maint_init()
1484 dma_free_coherent(&priv->pdev->dev, in tsi721_bdma_maint_init()
1487 priv->mdma.bd_base = NULL; in tsi721_bdma_maint_init()
1488 return -ENOMEM; in tsi721_bdma_maint_init()
1491 priv->mdma.sts_phys = sts_phys; in tsi721_bdma_maint_init()
1492 priv->mdma.sts_base = sts_ptr; in tsi721_bdma_maint_init()
1493 priv->mdma.sts_size = sts_size; in tsi721_bdma_maint_init()
1495 tsi_debug(MAINT, &priv->pdev->dev, in tsi721_bdma_maint_init()
1500 bd_ptr[bd_num - 1].type_id = cpu_to_le32(DTYPE3 << 29); in tsi721_bdma_maint_init()
1501 bd_ptr[bd_num - 1].next_lo = cpu_to_le32((u64)bd_phys & in tsi721_bdma_maint_init()
1503 bd_ptr[bd_num - 1].next_hi = cpu_to_le32((u64)bd_phys >> 32); in tsi721_bdma_maint_init()
1533 struct tsi721_bdma_maint *mdma = &priv->mdma; in tsi721_bdma_maint_free()
1534 void __iomem *regs = priv->regs + TSI721_DMAC_BASE(mdma->ch_id); in tsi721_bdma_maint_free()
1536 if (mdma->bd_base == NULL) in tsi721_bdma_maint_free()
1542 return -EFAULT; in tsi721_bdma_maint_free()
1548 dma_free_coherent(&priv->pdev->dev, in tsi721_bdma_maint_free()
1549 mdma->bd_num * sizeof(struct tsi721_dma_desc), in tsi721_bdma_maint_free()
1550 mdma->bd_base, mdma->bd_phys); in tsi721_bdma_maint_free()
1551 mdma->bd_base = NULL; in tsi721_bdma_maint_free()
1554 dma_free_coherent(&priv->pdev->dev, in tsi721_bdma_maint_free()
1555 mdma->sts_size * sizeof(struct tsi721_dma_sts), in tsi721_bdma_maint_free()
1556 mdma->sts_base, mdma->sts_phys); in tsi721_bdma_maint_free()
1557 mdma->sts_base = NULL; in tsi721_bdma_maint_free()
1572 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); in tsi721_imsg_interrupt_enable()
1575 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); in tsi721_imsg_interrupt_enable()
1576 iowrite32(rval | inte_mask, priv->regs + TSI721_IBDMAC_INTE(ch)); in tsi721_imsg_interrupt_enable()
1578 if (priv->flags & TSI721_USING_MSIX) in tsi721_imsg_interrupt_enable()
1579 return; /* Finished if we are in MSI-X mode */ in tsi721_imsg_interrupt_enable()
1586 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_interrupt_enable()
1588 priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_interrupt_enable()
1602 iowrite32(inte_mask, priv->regs + TSI721_IBDMAC_INT(ch)); in tsi721_imsg_interrupt_disable()
1605 rval = ioread32(priv->regs + TSI721_IBDMAC_INTE(ch)); in tsi721_imsg_interrupt_disable()
1607 iowrite32(rval, priv->regs + TSI721_IBDMAC_INTE(ch)); in tsi721_imsg_interrupt_disable()
1609 if (priv->flags & TSI721_USING_MSIX) in tsi721_imsg_interrupt_disable()
1610 return; /* Finished if we are in MSI-X mode */ in tsi721_imsg_interrupt_disable()
1617 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_interrupt_disable()
1619 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_interrupt_disable()
1622 /* Enable Outbound Messaging interrupts */
1632 /* Clear pending Outbound Messaging interrupts */ in tsi721_omsg_interrupt_enable()
1633 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); in tsi721_omsg_interrupt_enable()
1635 /* Enable Outbound Messaging channel interrupts */ in tsi721_omsg_interrupt_enable()
1636 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); in tsi721_omsg_interrupt_enable()
1637 iowrite32(rval | inte_mask, priv->regs + TSI721_OBDMAC_INTE(ch)); in tsi721_omsg_interrupt_enable()
1639 if (priv->flags & TSI721_USING_MSIX) in tsi721_omsg_interrupt_enable()
1640 return; /* Finished if we are in MSI-X mode */ in tsi721_omsg_interrupt_enable()
1647 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_interrupt_enable()
1649 priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_interrupt_enable()
1652 /* Disable Outbound Messaging interrupts */
1662 /* Clear pending Outbound Messaging interrupts */ in tsi721_omsg_interrupt_disable()
1663 iowrite32(inte_mask, priv->regs + TSI721_OBDMAC_INT(ch)); in tsi721_omsg_interrupt_disable()
1665 /* Disable Outbound Messaging interrupts */ in tsi721_omsg_interrupt_disable()
1666 rval = ioread32(priv->regs + TSI721_OBDMAC_INTE(ch)); in tsi721_omsg_interrupt_disable()
1668 iowrite32(rval, priv->regs + TSI721_OBDMAC_INTE(ch)); in tsi721_omsg_interrupt_disable()
1670 if (priv->flags & TSI721_USING_MSIX) in tsi721_omsg_interrupt_disable()
1671 return; /* Finished if we are in MSI-X mode */ in tsi721_omsg_interrupt_disable()
1678 rval = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_interrupt_disable()
1680 iowrite32(rval, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_interrupt_disable()
1684 * tsi721_add_outb_message - Add message to the Tsi721 outbound message queue
1685 * @mport: Master port with outbound message queue
1686 * @rdev: Target of outbound message
1687 * @mbox: Outbound mailbox
1688 * @buffer: Message to add to outbound queue
1691 * Returns: %0 on success or -errno value on failure.
1697 struct tsi721_device *priv = mport->priv; in tsi721_add_outb_message()
1702 if (!priv->omsg_init[mbox] || in tsi721_add_outb_message()
1704 return -EINVAL; in tsi721_add_outb_message()
1706 spin_lock_irqsave(&priv->omsg_ring[mbox].lock, flags); in tsi721_add_outb_message()
1708 tx_slot = priv->omsg_ring[mbox].tx_slot; in tsi721_add_outb_message()
1711 memcpy(priv->omsg_ring[mbox].omq_base[tx_slot], buffer, len); in tsi721_add_outb_message()
1717 desc = priv->omsg_ring[mbox].omd_base; in tsi721_add_outb_message()
1718 desc[tx_slot].type_id = cpu_to_le32((DTYPE4 << 29) | rdev->destid); in tsi721_add_outb_message()
1720 /* Request IOF_DONE interrupt generation for each N-th frame in queue */ in tsi721_add_outb_message()
1725 cpu_to_le32((mport->sys_size << 26) | (mbox << 22) | in tsi721_add_outb_message()
1728 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] & in tsi721_add_outb_message()
1731 cpu_to_le32((u64)priv->omsg_ring[mbox].omq_phys[tx_slot] >> 32); in tsi721_add_outb_message()
1733 priv->omsg_ring[mbox].wr_count++; in tsi721_add_outb_message()
1736 if (++priv->omsg_ring[mbox].tx_slot == priv->omsg_ring[mbox].size) { in tsi721_add_outb_message()
1737 priv->omsg_ring[mbox].tx_slot = 0; in tsi721_add_outb_message()
1739 priv->omsg_ring[mbox].wr_count++; in tsi721_add_outb_message()
1745 iowrite32(priv->omsg_ring[mbox].wr_count, in tsi721_add_outb_message()
1746 priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); in tsi721_add_outb_message()
1747 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); in tsi721_add_outb_message()
1749 spin_unlock_irqrestore(&priv->omsg_ring[mbox].lock, flags); in tsi721_add_outb_message()
1755 * tsi721_omsg_handler - Outbound Message Interrupt Handler
1759 * Services channel interrupts from outbound messaging engine.
1764 struct rio_mport *mport = &priv->mport; in tsi721_omsg_handler()
1769 spin_lock(&priv->omsg_ring[ch].lock); in tsi721_omsg_handler()
1771 omsg_int = ioread32(priv->regs + TSI721_OBDMAC_INT(ch)); in tsi721_omsg_handler()
1774 tsi_info(&priv->pdev->dev, in tsi721_omsg_handler()
1787 srd_ptr = priv->omsg_ring[ch].sts_rdptr; in tsi721_omsg_handler()
1788 sts_ptr = priv->omsg_ring[ch].sts_base; in tsi721_omsg_handler()
1798 srd_ptr %= priv->omsg_ring[ch].sts_size; in tsi721_omsg_handler()
1805 priv->omsg_ring[ch].sts_rdptr = srd_ptr; in tsi721_omsg_handler()
1806 iowrite32(srd_ptr, priv->regs + TSI721_OBDMAC_DSRP(ch)); in tsi721_omsg_handler()
1808 if (!mport->outb_msg[ch].mcback) in tsi721_omsg_handler()
1813 tx_slot = (last_ptr - (u64)priv->omsg_ring[ch].omd_phys)/ in tsi721_omsg_handler()
1821 if (tx_slot == priv->omsg_ring[ch].size) { in tsi721_omsg_handler()
1823 tx_slot = (prev_ptr - in tsi721_omsg_handler()
1824 (u64)priv->omsg_ring[ch].omd_phys)/ in tsi721_omsg_handler()
1830 if (tx_slot >= priv->omsg_ring[ch].size) in tsi721_omsg_handler()
1831 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_omsg_handler()
1833 tx_slot, priv->omsg_ring[ch].size); in tsi721_omsg_handler()
1834 WARN_ON(tx_slot >= priv->omsg_ring[ch].size); in tsi721_omsg_handler()
1838 if (tx_slot == priv->omsg_ring[ch].size) in tsi721_omsg_handler()
1841 dev_id = priv->omsg_ring[ch].dev_id; in tsi721_omsg_handler()
1849 * Outbound message operation aborted due to error, in tsi721_omsg_handler()
1853 tsi_debug(OMSG, &priv->pdev->dev, "OB MSG ABORT ch_stat=%x", in tsi721_omsg_handler()
1854 ioread32(priv->regs + TSI721_OBDMAC_STS(ch))); in tsi721_omsg_handler()
1857 priv->regs + TSI721_OBDMAC_INT(ch)); in tsi721_omsg_handler()
1859 priv->regs + TSI721_OBDMAC_CTL(ch)); in tsi721_omsg_handler()
1860 ioread32(priv->regs + TSI721_OBDMAC_CTL(ch)); in tsi721_omsg_handler()
1863 dev_id = priv->omsg_ring[ch].dev_id; in tsi721_omsg_handler()
1864 tx_slot = priv->omsg_ring[ch].tx_slot; in tsi721_omsg_handler()
1868 iowrite32(priv->omsg_ring[ch].tx_slot, in tsi721_omsg_handler()
1869 priv->regs + TSI721_OBDMAC_DRDCNT(ch)); in tsi721_omsg_handler()
1870 ioread32(priv->regs + TSI721_OBDMAC_DRDCNT(ch)); in tsi721_omsg_handler()
1871 priv->omsg_ring[ch].wr_count = priv->omsg_ring[ch].tx_slot; in tsi721_omsg_handler()
1872 priv->omsg_ring[ch].sts_rdptr = 0; in tsi721_omsg_handler()
1876 iowrite32(omsg_int, priv->regs + TSI721_OBDMAC_INT(ch)); in tsi721_omsg_handler()
1878 if (!(priv->flags & TSI721_USING_MSIX)) { in tsi721_omsg_handler()
1881 /* Re-enable channel interrupts */ in tsi721_omsg_handler()
1882 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_handler()
1884 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_omsg_handler()
1887 spin_unlock(&priv->omsg_ring[ch].lock); in tsi721_omsg_handler()
1889 if (mport->outb_msg[ch].mcback && do_callback) in tsi721_omsg_handler()
1890 mport->outb_msg[ch].mcback(mport, dev_id, ch, tx_slot); in tsi721_omsg_handler()
1894 * tsi721_open_outb_mbox - Initialize Tsi721 outbound mailbox
1895 * @mport: Master port implementing Outbound Messaging Engine
1898 * @entries: Number of entries in the outbound mailbox ring
1900 * Returns: %0 on success or -errno value on failure.
1905 struct tsi721_device *priv = mport->priv; in tsi721_open_outb_mbox()
1912 rc = -EINVAL; in tsi721_open_outb_mbox()
1917 rc = -ENODEV; in tsi721_open_outb_mbox()
1921 priv->omsg_ring[mbox].dev_id = dev_id; in tsi721_open_outb_mbox()
1922 priv->omsg_ring[mbox].size = entries; in tsi721_open_outb_mbox()
1923 priv->omsg_ring[mbox].sts_rdptr = 0; in tsi721_open_outb_mbox()
1924 spin_lock_init(&priv->omsg_ring[mbox].lock); in tsi721_open_outb_mbox()
1926 /* Outbound Msg Buffer allocation based on in tsi721_open_outb_mbox()
1929 priv->omsg_ring[mbox].omq_base[i] = in tsi721_open_outb_mbox()
1931 &priv->pdev->dev, TSI721_MSG_BUFFER_SIZE, in tsi721_open_outb_mbox()
1932 &priv->omsg_ring[mbox].omq_phys[i], in tsi721_open_outb_mbox()
1934 if (priv->omsg_ring[mbox].omq_base[i] == NULL) { in tsi721_open_outb_mbox()
1935 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_open_outb_mbox()
1937 rc = -ENOMEM; in tsi721_open_outb_mbox()
1942 /* Outbound message descriptor allocation */ in tsi721_open_outb_mbox()
1943 priv->omsg_ring[mbox].omd_base = dma_alloc_coherent( in tsi721_open_outb_mbox()
1944 &priv->pdev->dev, in tsi721_open_outb_mbox()
1946 &priv->omsg_ring[mbox].omd_phys, GFP_KERNEL); in tsi721_open_outb_mbox()
1947 if (priv->omsg_ring[mbox].omd_base == NULL) { in tsi721_open_outb_mbox()
1948 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_open_outb_mbox()
1950 rc = -ENOMEM; in tsi721_open_outb_mbox()
1954 priv->omsg_ring[mbox].tx_slot = 0; in tsi721_open_outb_mbox()
1956 /* Outbound message descriptor status FIFO allocation */ in tsi721_open_outb_mbox()
1957 priv->omsg_ring[mbox].sts_size = roundup_pow_of_two(entries + 1); in tsi721_open_outb_mbox()
1958 priv->omsg_ring[mbox].sts_base = dma_alloc_coherent(&priv->pdev->dev, in tsi721_open_outb_mbox()
1959 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), in tsi721_open_outb_mbox()
1960 &priv->omsg_ring[mbox].sts_phys, in tsi721_open_outb_mbox()
1962 if (priv->omsg_ring[mbox].sts_base == NULL) { in tsi721_open_outb_mbox()
1963 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_open_outb_mbox()
1965 rc = -ENOMEM; in tsi721_open_outb_mbox()
1970 * Configure Outbound Messaging Engine in tsi721_open_outb_mbox()
1973 /* Setup Outbound Message descriptor pointer */ in tsi721_open_outb_mbox()
1974 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys >> 32), in tsi721_open_outb_mbox()
1975 priv->regs + TSI721_OBDMAC_DPTRH(mbox)); in tsi721_open_outb_mbox()
1976 iowrite32(((u64)priv->omsg_ring[mbox].omd_phys & in tsi721_open_outb_mbox()
1978 priv->regs + TSI721_OBDMAC_DPTRL(mbox)); in tsi721_open_outb_mbox()
1980 /* Setup Outbound Message descriptor status FIFO */ in tsi721_open_outb_mbox()
1981 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys >> 32), in tsi721_open_outb_mbox()
1982 priv->regs + TSI721_OBDMAC_DSBH(mbox)); in tsi721_open_outb_mbox()
1983 iowrite32(((u64)priv->omsg_ring[mbox].sts_phys & in tsi721_open_outb_mbox()
1985 priv->regs + TSI721_OBDMAC_DSBL(mbox)); in tsi721_open_outb_mbox()
1986 iowrite32(TSI721_DMAC_DSSZ_SIZE(priv->omsg_ring[mbox].sts_size), in tsi721_open_outb_mbox()
1987 priv->regs + (u32)TSI721_OBDMAC_DSSZ(mbox)); in tsi721_open_outb_mbox()
1992 if (priv->flags & TSI721_USING_MSIX) { in tsi721_open_outb_mbox()
1995 /* Request interrupt service if we are in MSI-X mode */ in tsi721_open_outb_mbox()
1996 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, in tsi721_open_outb_mbox()
1997 priv->msix[idx].irq_name, (void *)priv); in tsi721_open_outb_mbox()
2000 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_open_outb_mbox()
2001 "Unable to get MSI-X IRQ for OBOX%d-DONE", in tsi721_open_outb_mbox()
2007 rc = request_irq(priv->msix[idx].vector, tsi721_omsg_msix, 0, in tsi721_open_outb_mbox()
2008 priv->msix[idx].irq_name, (void *)priv); in tsi721_open_outb_mbox()
2011 tsi_debug(OMSG, &priv->pdev->dev, in tsi721_open_outb_mbox()
2012 "Unable to get MSI-X IRQ for MBOX%d-INT", mbox); in tsi721_open_outb_mbox()
2014 free_irq(priv->msix[idx].vector, (void *)priv); in tsi721_open_outb_mbox()
2022 /* Initialize Outbound Message descriptors ring */ in tsi721_open_outb_mbox()
2023 bd_ptr = priv->omsg_ring[mbox].omd_base; in tsi721_open_outb_mbox()
2027 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys & in tsi721_open_outb_mbox()
2030 cpu_to_le32((u64)priv->omsg_ring[mbox].omd_phys >> 32); in tsi721_open_outb_mbox()
2031 priv->omsg_ring[mbox].wr_count = 0; in tsi721_open_outb_mbox()
2034 /* Initialize Outbound Message engine */ in tsi721_open_outb_mbox()
2036 priv->regs + TSI721_OBDMAC_CTL(mbox)); in tsi721_open_outb_mbox()
2037 ioread32(priv->regs + TSI721_OBDMAC_DWRCNT(mbox)); in tsi721_open_outb_mbox()
2040 priv->omsg_init[mbox] = 1; in tsi721_open_outb_mbox()
2046 dma_free_coherent(&priv->pdev->dev, in tsi721_open_outb_mbox()
2047 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), in tsi721_open_outb_mbox()
2048 priv->omsg_ring[mbox].sts_base, in tsi721_open_outb_mbox()
2049 priv->omsg_ring[mbox].sts_phys); in tsi721_open_outb_mbox()
2051 priv->omsg_ring[mbox].sts_base = NULL; in tsi721_open_outb_mbox()
2055 dma_free_coherent(&priv->pdev->dev, in tsi721_open_outb_mbox()
2057 priv->omsg_ring[mbox].omd_base, in tsi721_open_outb_mbox()
2058 priv->omsg_ring[mbox].omd_phys); in tsi721_open_outb_mbox()
2060 priv->omsg_ring[mbox].omd_base = NULL; in tsi721_open_outb_mbox()
2063 for (i = 0; i < priv->omsg_ring[mbox].size; i++) { in tsi721_open_outb_mbox()
2064 if (priv->omsg_ring[mbox].omq_base[i]) { in tsi721_open_outb_mbox()
2065 dma_free_coherent(&priv->pdev->dev, in tsi721_open_outb_mbox()
2067 priv->omsg_ring[mbox].omq_base[i], in tsi721_open_outb_mbox()
2068 priv->omsg_ring[mbox].omq_phys[i]); in tsi721_open_outb_mbox()
2070 priv->omsg_ring[mbox].omq_base[i] = NULL; in tsi721_open_outb_mbox()
2079 * tsi721_close_outb_mbox - Close Tsi721 outbound mailbox
2080 * @mport: Master port implementing the outbound message unit
2085 struct tsi721_device *priv = mport->priv; in tsi721_close_outb_mbox()
2088 if (!priv->omsg_init[mbox]) in tsi721_close_outb_mbox()
2090 priv->omsg_init[mbox] = 0; in tsi721_close_outb_mbox()
2097 if (priv->flags & TSI721_USING_MSIX) { in tsi721_close_outb_mbox()
2098 free_irq(priv->msix[TSI721_VECT_OMB0_DONE + mbox].vector, in tsi721_close_outb_mbox()
2100 free_irq(priv->msix[TSI721_VECT_OMB0_INT + mbox].vector, in tsi721_close_outb_mbox()
2106 dma_free_coherent(&priv->pdev->dev, in tsi721_close_outb_mbox()
2107 priv->omsg_ring[mbox].sts_size * sizeof(struct tsi721_dma_sts), in tsi721_close_outb_mbox()
2108 priv->omsg_ring[mbox].sts_base, in tsi721_close_outb_mbox()
2109 priv->omsg_ring[mbox].sts_phys); in tsi721_close_outb_mbox()
2111 priv->omsg_ring[mbox].sts_base = NULL; in tsi721_close_outb_mbox()
2114 dma_free_coherent(&priv->pdev->dev, in tsi721_close_outb_mbox()
2115 (priv->omsg_ring[mbox].size + 1) * in tsi721_close_outb_mbox()
2117 priv->omsg_ring[mbox].omd_base, in tsi721_close_outb_mbox()
2118 priv->omsg_ring[mbox].omd_phys); in tsi721_close_outb_mbox()
2120 priv->omsg_ring[mbox].omd_base = NULL; in tsi721_close_outb_mbox()
2123 for (i = 0; i < priv->omsg_ring[mbox].size; i++) { in tsi721_close_outb_mbox()
2124 if (priv->omsg_ring[mbox].omq_base[i]) { in tsi721_close_outb_mbox()
2125 dma_free_coherent(&priv->pdev->dev, in tsi721_close_outb_mbox()
2127 priv->omsg_ring[mbox].omq_base[i], in tsi721_close_outb_mbox()
2128 priv->omsg_ring[mbox].omq_phys[i]); in tsi721_close_outb_mbox()
2130 priv->omsg_ring[mbox].omq_base[i] = NULL; in tsi721_close_outb_mbox()
2136 * tsi721_imsg_handler - Inbound Message Interrupt Handler
2144 u32 mbox = ch - 4; in tsi721_imsg_handler()
2146 struct rio_mport *mport = &priv->mport; in tsi721_imsg_handler()
2148 spin_lock(&priv->imsg_ring[mbox].lock); in tsi721_imsg_handler()
2150 imsg_int = ioread32(priv->regs + TSI721_IBDMAC_INT(ch)); in tsi721_imsg_handler()
2153 tsi_info(&priv->pdev->dev, "IB MBOX%d SRIO timeout", mbox); in tsi721_imsg_handler()
2156 tsi_info(&priv->pdev->dev, "IB MBOX%d PCIe error", mbox); in tsi721_imsg_handler()
2159 tsi_info(&priv->pdev->dev, "IB MBOX%d IB free queue low", mbox); in tsi721_imsg_handler()
2162 iowrite32(imsg_int, priv->regs + TSI721_IBDMAC_INT(ch)); in tsi721_imsg_handler()
2166 mport->inb_msg[mbox].mcback) in tsi721_imsg_handler()
2167 mport->inb_msg[mbox].mcback(mport, in tsi721_imsg_handler()
2168 priv->imsg_ring[mbox].dev_id, mbox, -1); in tsi721_imsg_handler()
2170 if (!(priv->flags & TSI721_USING_MSIX)) { in tsi721_imsg_handler()
2173 /* Re-enable channel interrupts */ in tsi721_imsg_handler()
2174 ch_inte = ioread32(priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_handler()
2176 iowrite32(ch_inte, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_imsg_handler()
2179 spin_unlock(&priv->imsg_ring[mbox].lock); in tsi721_imsg_handler()
2183 * tsi721_open_inb_mbox - Initialize Tsi721 inbound mailbox
2189 * Returns: %0 on success or -errno value on failure.
2194 struct tsi721_device *priv = mport->priv; in tsi721_open_inb_mbox()
2203 rc = -EINVAL; in tsi721_open_inb_mbox()
2208 rc = -ENODEV; in tsi721_open_inb_mbox()
2213 priv->imsg_ring[mbox].dev_id = dev_id; in tsi721_open_inb_mbox()
2214 priv->imsg_ring[mbox].size = entries; in tsi721_open_inb_mbox()
2215 priv->imsg_ring[mbox].rx_slot = 0; in tsi721_open_inb_mbox()
2216 priv->imsg_ring[mbox].desc_rdptr = 0; in tsi721_open_inb_mbox()
2217 priv->imsg_ring[mbox].fq_wrptr = 0; in tsi721_open_inb_mbox()
2218 for (i = 0; i < priv->imsg_ring[mbox].size; i++) in tsi721_open_inb_mbox()
2219 priv->imsg_ring[mbox].imq_base[i] = NULL; in tsi721_open_inb_mbox()
2220 spin_lock_init(&priv->imsg_ring[mbox].lock); in tsi721_open_inb_mbox()
2223 priv->imsg_ring[mbox].buf_base = in tsi721_open_inb_mbox()
2224 dma_alloc_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2226 &priv->imsg_ring[mbox].buf_phys, in tsi721_open_inb_mbox()
2229 if (priv->imsg_ring[mbox].buf_base == NULL) { in tsi721_open_inb_mbox()
2230 tsi_err(&priv->pdev->dev, in tsi721_open_inb_mbox()
2232 rc = -ENOMEM; in tsi721_open_inb_mbox()
2237 priv->imsg_ring[mbox].imfq_base = in tsi721_open_inb_mbox()
2238 dma_alloc_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2240 &priv->imsg_ring[mbox].imfq_phys, in tsi721_open_inb_mbox()
2243 if (priv->imsg_ring[mbox].imfq_base == NULL) { in tsi721_open_inb_mbox()
2244 tsi_err(&priv->pdev->dev, in tsi721_open_inb_mbox()
2246 rc = -ENOMEM; in tsi721_open_inb_mbox()
2251 priv->imsg_ring[mbox].imd_base = in tsi721_open_inb_mbox()
2252 dma_alloc_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2254 &priv->imsg_ring[mbox].imd_phys, GFP_KERNEL); in tsi721_open_inb_mbox()
2256 if (priv->imsg_ring[mbox].imd_base == NULL) { in tsi721_open_inb_mbox()
2257 tsi_err(&priv->pdev->dev, in tsi721_open_inb_mbox()
2260 rc = -ENOMEM; in tsi721_open_inb_mbox()
2265 free_ptr = priv->imsg_ring[mbox].imfq_base; in tsi721_open_inb_mbox()
2268 (u64)(priv->imsg_ring[mbox].buf_phys) + in tsi721_open_inb_mbox()
2278 if (!(priv->flags & TSI721_IMSGID_SET)) { in tsi721_open_inb_mbox()
2279 iowrite32((u32)priv->mport.host_deviceid, in tsi721_open_inb_mbox()
2280 priv->regs + TSI721_IB_DEVID); in tsi721_open_inb_mbox()
2281 priv->flags |= TSI721_IMSGID_SET; in tsi721_open_inb_mbox()
2289 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys >> 32), in tsi721_open_inb_mbox()
2290 priv->regs + TSI721_IBDMAC_FQBH(ch)); in tsi721_open_inb_mbox()
2291 iowrite32(((u64)priv->imsg_ring[mbox].imfq_phys & in tsi721_open_inb_mbox()
2293 priv->regs+TSI721_IBDMAC_FQBL(ch)); in tsi721_open_inb_mbox()
2295 priv->regs + TSI721_IBDMAC_FQSZ(ch)); in tsi721_open_inb_mbox()
2298 iowrite32(((u64)priv->imsg_ring[mbox].imd_phys >> 32), in tsi721_open_inb_mbox()
2299 priv->regs + TSI721_IBDMAC_DQBH(ch)); in tsi721_open_inb_mbox()
2300 iowrite32(((u32)priv->imsg_ring[mbox].imd_phys & in tsi721_open_inb_mbox()
2302 priv->regs+TSI721_IBDMAC_DQBL(ch)); in tsi721_open_inb_mbox()
2304 priv->regs + TSI721_IBDMAC_DQSZ(ch)); in tsi721_open_inb_mbox()
2309 if (priv->flags & TSI721_USING_MSIX) { in tsi721_open_inb_mbox()
2312 /* Request interrupt service if we are in MSI-X mode */ in tsi721_open_inb_mbox()
2313 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, in tsi721_open_inb_mbox()
2314 priv->msix[idx].irq_name, (void *)priv); in tsi721_open_inb_mbox()
2317 tsi_debug(IMSG, &priv->pdev->dev, in tsi721_open_inb_mbox()
2318 "Unable to get MSI-X IRQ for IBOX%d-DONE", in tsi721_open_inb_mbox()
2324 rc = request_irq(priv->msix[idx].vector, tsi721_imsg_msix, 0, in tsi721_open_inb_mbox()
2325 priv->msix[idx].irq_name, (void *)priv); in tsi721_open_inb_mbox()
2328 tsi_debug(IMSG, &priv->pdev->dev, in tsi721_open_inb_mbox()
2329 "Unable to get MSI-X IRQ for IBOX%d-INT", mbox); in tsi721_open_inb_mbox()
2331 priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, in tsi721_open_inb_mbox()
2341 iowrite32(TSI721_IBDMAC_CTL_INIT, priv->regs + TSI721_IBDMAC_CTL(ch)); in tsi721_open_inb_mbox()
2342 ioread32(priv->regs + TSI721_IBDMAC_CTL(ch)); in tsi721_open_inb_mbox()
2344 priv->imsg_ring[mbox].fq_wrptr = entries - 1; in tsi721_open_inb_mbox()
2345 iowrite32(entries - 1, priv->regs + TSI721_IBDMAC_FQWP(ch)); in tsi721_open_inb_mbox()
2347 priv->imsg_init[mbox] = 1; in tsi721_open_inb_mbox()
2352 dma_free_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2353 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), in tsi721_open_inb_mbox()
2354 priv->imsg_ring[mbox].imd_base, in tsi721_open_inb_mbox()
2355 priv->imsg_ring[mbox].imd_phys); in tsi721_open_inb_mbox()
2357 priv->imsg_ring[mbox].imd_base = NULL; in tsi721_open_inb_mbox()
2361 dma_free_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2362 priv->imsg_ring[mbox].size * 8, in tsi721_open_inb_mbox()
2363 priv->imsg_ring[mbox].imfq_base, in tsi721_open_inb_mbox()
2364 priv->imsg_ring[mbox].imfq_phys); in tsi721_open_inb_mbox()
2366 priv->imsg_ring[mbox].imfq_base = NULL; in tsi721_open_inb_mbox()
2369 dma_free_coherent(&priv->pdev->dev, in tsi721_open_inb_mbox()
2370 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, in tsi721_open_inb_mbox()
2371 priv->imsg_ring[mbox].buf_base, in tsi721_open_inb_mbox()
2372 priv->imsg_ring[mbox].buf_phys); in tsi721_open_inb_mbox()
2374 priv->imsg_ring[mbox].buf_base = NULL; in tsi721_open_inb_mbox()
2381 * tsi721_close_inb_mbox - Shut down Tsi721 inbound mailbox
2387 struct tsi721_device *priv = mport->priv; in tsi721_close_inb_mbox()
2391 if (!priv->imsg_init[mbox]) /* mbox isn't initialized yet */ in tsi721_close_inb_mbox()
2393 priv->imsg_init[mbox] = 0; in tsi721_close_inb_mbox()
2401 if (priv->flags & TSI721_USING_MSIX) { in tsi721_close_inb_mbox()
2402 free_irq(priv->msix[TSI721_VECT_IMB0_RCV + mbox].vector, in tsi721_close_inb_mbox()
2404 free_irq(priv->msix[TSI721_VECT_IMB0_INT + mbox].vector, in tsi721_close_inb_mbox()
2410 for (rx_slot = 0; rx_slot < priv->imsg_ring[mbox].size; rx_slot++) in tsi721_close_inb_mbox()
2411 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; in tsi721_close_inb_mbox()
2414 dma_free_coherent(&priv->pdev->dev, in tsi721_close_inb_mbox()
2415 priv->imsg_ring[mbox].size * TSI721_MSG_BUFFER_SIZE, in tsi721_close_inb_mbox()
2416 priv->imsg_ring[mbox].buf_base, in tsi721_close_inb_mbox()
2417 priv->imsg_ring[mbox].buf_phys); in tsi721_close_inb_mbox()
2419 priv->imsg_ring[mbox].buf_base = NULL; in tsi721_close_inb_mbox()
2422 dma_free_coherent(&priv->pdev->dev, in tsi721_close_inb_mbox()
2423 priv->imsg_ring[mbox].size * 8, in tsi721_close_inb_mbox()
2424 priv->imsg_ring[mbox].imfq_base, in tsi721_close_inb_mbox()
2425 priv->imsg_ring[mbox].imfq_phys); in tsi721_close_inb_mbox()
2427 priv->imsg_ring[mbox].imfq_base = NULL; in tsi721_close_inb_mbox()
2430 dma_free_coherent(&priv->pdev->dev, in tsi721_close_inb_mbox()
2431 priv->imsg_ring[mbox].size * sizeof(struct tsi721_imsg_desc), in tsi721_close_inb_mbox()
2432 priv->imsg_ring[mbox].imd_base, in tsi721_close_inb_mbox()
2433 priv->imsg_ring[mbox].imd_phys); in tsi721_close_inb_mbox()
2435 priv->imsg_ring[mbox].imd_base = NULL; in tsi721_close_inb_mbox()
2439 * tsi721_add_inb_buffer - Add buffer to the Tsi721 inbound message queue
2444 * Returns: %0 on success or -errno value on failure.
2448 struct tsi721_device *priv = mport->priv; in tsi721_add_inb_buffer()
2452 rx_slot = priv->imsg_ring[mbox].rx_slot; in tsi721_add_inb_buffer()
2453 if (priv->imsg_ring[mbox].imq_base[rx_slot]) { in tsi721_add_inb_buffer()
2454 tsi_err(&priv->pdev->dev, in tsi721_add_inb_buffer()
2457 rc = -EINVAL; in tsi721_add_inb_buffer()
2461 priv->imsg_ring[mbox].imq_base[rx_slot] = buf; in tsi721_add_inb_buffer()
2463 if (++priv->imsg_ring[mbox].rx_slot == priv->imsg_ring[mbox].size) in tsi721_add_inb_buffer()
2464 priv->imsg_ring[mbox].rx_slot = 0; in tsi721_add_inb_buffer()
2471 * tsi721_get_inb_message - Fetch inbound message from the Tsi721 MSG Queue
2479 struct tsi721_device *priv = mport->priv; in tsi721_get_inb_message()
2489 if (!priv->imsg_init[mbox]) in tsi721_get_inb_message()
2492 desc = priv->imsg_ring[mbox].imd_base; in tsi721_get_inb_message()
2493 desc += priv->imsg_ring[mbox].desc_rdptr; in tsi721_get_inb_message()
2495 if (!(le32_to_cpu(desc->msg_info) & TSI721_IMD_HO)) in tsi721_get_inb_message()
2498 rx_slot = priv->imsg_ring[mbox].rx_slot; in tsi721_get_inb_message()
2499 while (priv->imsg_ring[mbox].imq_base[rx_slot] == NULL) { in tsi721_get_inb_message()
2500 if (++rx_slot == priv->imsg_ring[mbox].size) in tsi721_get_inb_message()
2504 rx_phys = ((u64)le32_to_cpu(desc->bufptr_hi) << 32) | in tsi721_get_inb_message()
2505 le32_to_cpu(desc->bufptr_lo); in tsi721_get_inb_message()
2507 rx_virt = priv->imsg_ring[mbox].buf_base + in tsi721_get_inb_message()
2508 (rx_phys - (u64)priv->imsg_ring[mbox].buf_phys); in tsi721_get_inb_message()
2510 buf = priv->imsg_ring[mbox].imq_base[rx_slot]; in tsi721_get_inb_message()
2511 msg_size = le32_to_cpu(desc->msg_info) & TSI721_IMD_BCOUNT; in tsi721_get_inb_message()
2516 priv->imsg_ring[mbox].imq_base[rx_slot] = NULL; in tsi721_get_inb_message()
2518 desc->msg_info &= cpu_to_le32(~TSI721_IMD_HO); in tsi721_get_inb_message()
2519 if (++priv->imsg_ring[mbox].desc_rdptr == priv->imsg_ring[mbox].size) in tsi721_get_inb_message()
2520 priv->imsg_ring[mbox].desc_rdptr = 0; in tsi721_get_inb_message()
2522 iowrite32(priv->imsg_ring[mbox].desc_rdptr, in tsi721_get_inb_message()
2523 priv->regs + TSI721_IBDMAC_DQRP(ch)); in tsi721_get_inb_message()
2526 free_ptr = priv->imsg_ring[mbox].imfq_base; in tsi721_get_inb_message()
2527 free_ptr[priv->imsg_ring[mbox].fq_wrptr] = cpu_to_le64(rx_phys); in tsi721_get_inb_message()
2529 if (++priv->imsg_ring[mbox].fq_wrptr == priv->imsg_ring[mbox].size) in tsi721_get_inb_message()
2530 priv->imsg_ring[mbox].fq_wrptr = 0; in tsi721_get_inb_message()
2532 iowrite32(priv->imsg_ring[mbox].fq_wrptr, in tsi721_get_inb_message()
2533 priv->regs + TSI721_IBDMAC_FQWP(ch)); in tsi721_get_inb_message()
2539 * tsi721_messages_init - Initialization of Messaging Engine
2550 iowrite32(0, priv->regs + TSI721_SMSG_ECC_LOG); in tsi721_messages_init()
2551 iowrite32(0, priv->regs + TSI721_RETRY_GEN_CNT); in tsi721_messages_init()
2552 iowrite32(0, priv->regs + TSI721_RETRY_RX_CNT); in tsi721_messages_init()
2555 iowrite32(TSI721_RQRPTO_VAL, priv->regs + TSI721_RQRPTO); in tsi721_messages_init()
2561 priv->regs + TSI721_IBDMAC_INT(ch)); in tsi721_messages_init()
2563 iowrite32(0, priv->regs + TSI721_IBDMAC_STS(ch)); in tsi721_messages_init()
2566 priv->regs + TSI721_SMSG_ECC_COR_LOG(ch)); in tsi721_messages_init()
2568 priv->regs + TSI721_SMSG_ECC_NCOR(ch)); in tsi721_messages_init()
2575 * tsi721_query_mport - Fetch inbound message from the Tsi721 MSG Queue
2584 struct tsi721_device *priv = mport->priv; in tsi721_query_mport()
2587 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_ERR_STS_CSR(0, 0)); in tsi721_query_mport()
2589 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL2_CSR(0, 0)); in tsi721_query_mport()
2590 attr->link_speed = (rval & RIO_PORT_N_CTL2_SEL_BAUD) >> 28; in tsi721_query_mport()
2591 rval = ioread32(priv->regs + 0x100 + RIO_PORT_N_CTL_CSR(0, 0)); in tsi721_query_mport()
2592 attr->link_width = (rval & RIO_PORT_N_CTL_IPW) >> 27; in tsi721_query_mport()
2594 attr->link_speed = RIO_LINK_DOWN; in tsi721_query_mport()
2597 attr->flags = RIO_MPORT_DMA | RIO_MPORT_DMA_SG; in tsi721_query_mport()
2598 attr->dma_max_sge = 0; in tsi721_query_mport()
2599 attr->dma_max_size = TSI721_BDMA_MAX_BCOUNT; in tsi721_query_mport()
2600 attr->dma_align = 0; in tsi721_query_mport()
2602 attr->flags = 0; in tsi721_query_mport()
2608 * tsi721_disable_ints - disables all device interrupts
2616 iowrite32(0, priv->regs + TSI721_DEV_INTE); in tsi721_disable_ints()
2619 iowrite32(0, priv->regs + TSI721_DEV_CHAN_INTE); in tsi721_disable_ints()
2623 iowrite32(0, priv->regs + TSI721_IBDMAC_INTE(ch)); in tsi721_disable_ints()
2625 /* Disable all Outbound Msg Channel interrupts */ in tsi721_disable_ints()
2627 iowrite32(0, priv->regs + TSI721_OBDMAC_INTE(ch)); in tsi721_disable_ints()
2630 iowrite32(0, priv->regs + TSI721_SMSG_INTE); in tsi721_disable_ints()
2635 priv->regs + TSI721_DMAC_BASE(ch) + TSI721_DMAC_INTE); in tsi721_disable_ints()
2638 iowrite32(0, priv->regs + TSI721_BDMA_INTE); in tsi721_disable_ints()
2642 iowrite32(0, priv->regs + TSI721_SR_CHINTE(ch)); in tsi721_disable_ints()
2645 iowrite32(0, priv->regs + TSI721_SR2PC_GEN_INTE); in tsi721_disable_ints()
2648 iowrite32(0, priv->regs + TSI721_PC2SR_INTE); in tsi721_disable_ints()
2651 iowrite32(0, priv->regs + TSI721_I2C_INT_ENABLE); in tsi721_disable_ints()
2654 iowrite32(0, priv->regs + TSI721_RIO_EM_INT_ENABLE); in tsi721_disable_ints()
2655 iowrite32(0, priv->regs + TSI721_RIO_EM_DEV_INT_EN); in tsi721_disable_ints()
2683 tsi_debug(EXIT, dev, "%s id=%d", mport->name, mport->id); in tsi721_mport_release()
2687 * tsi721_setup_mport - Setup Tsi721 as RapidIO subsystem master port
2692 * Returns: %0 on success or -errno value on failure.
2696 struct pci_dev *pdev = priv->pdev; in tsi721_setup_mport()
2698 struct rio_mport *mport = &priv->mport; in tsi721_setup_mport()
2704 mport->ops = &tsi721_rio_ops; in tsi721_setup_mport()
2705 mport->index = 0; in tsi721_setup_mport()
2706 mport->sys_size = 0; /* small system */ in tsi721_setup_mport()
2707 mport->priv = (void *)priv; in tsi721_setup_mport()
2708 mport->phys_efptr = 0x100; in tsi721_setup_mport()
2709 mport->phys_rmap = 1; in tsi721_setup_mport()
2710 mport->dev.parent = &pdev->dev; in tsi721_setup_mport()
2711 mport->dev.release = tsi721_mport_release; in tsi721_setup_mport()
2713 INIT_LIST_HEAD(&mport->dbells); in tsi721_setup_mport()
2715 rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff); in tsi721_setup_mport()
2716 rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 3); in tsi721_setup_mport()
2717 rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 3); in tsi721_setup_mport()
2718 snprintf(mport->name, RIO_MAX_MPORT_NAME, "%s(%s)", in tsi721_setup_mport()
2719 dev_driver_string(&pdev->dev), dev_name(&pdev->dev)); in tsi721_setup_mport()
2725 priv->flags |= TSI721_USING_MSIX; in tsi721_setup_mport()
2727 priv->flags |= TSI721_USING_MSI; in tsi721_setup_mport()
2729 tsi_debug(MPORT, &pdev->dev, in tsi721_setup_mport()
2730 "MSI/MSI-X is not available. Using legacy INTx."); in tsi721_setup_mport()
2736 tsi_err(&pdev->dev, "Unable to get PCI IRQ %02X (err=0x%x)", in tsi721_setup_mport()
2737 pdev->irq, err); in tsi721_setup_mport()
2747 iowrite32(ioread32(priv->regs + TSI721_DEVCTL) | in tsi721_setup_mport()
2749 priv->regs + TSI721_DEVCTL); in tsi721_setup_mport()
2751 if (mport->host_deviceid >= 0) in tsi721_setup_mport()
2754 priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); in tsi721_setup_mport()
2756 iowrite32(0, priv->regs + (0x100 + RIO_PORT_GEN_CTL_CSR)); in tsi721_setup_mport()
2779 err = -ENOMEM; in tsi721_probe()
2785 tsi_err(&pdev->dev, "Failed to enable PCI device"); in tsi721_probe()
2789 priv->pdev = pdev; in tsi721_probe()
2796 tsi_debug(INIT, &pdev->dev, "res%d %pR", in tsi721_probe()
2797 i, &pdev->resource[i]); in tsi721_probe()
2805 /* BAR_0 (registers) must be 512KB+ in 32-bit address space */ in tsi721_probe()
2809 tsi_err(&pdev->dev, "Missing or misconfigured CSR BAR0"); in tsi721_probe()
2810 err = -ENODEV; in tsi721_probe()
2814 /* BAR_1 (outbound doorbells) must be 16MB+ in 32-bit address space */ in tsi721_probe()
2818 tsi_err(&pdev->dev, "Missing or misconfigured Doorbell BAR1"); in tsi721_probe()
2819 err = -ENODEV; in tsi721_probe()
2824 * BAR_2 and BAR_4 (outbound translation) must be in 64-bit PCIe address in tsi721_probe()
2831 priv->p2r_bar[0].size = priv->p2r_bar[1].size = 0; in tsi721_probe()
2835 tsi_debug(INIT, &pdev->dev, in tsi721_probe()
2838 priv->p2r_bar[0].base = pci_resource_start(pdev, BAR_2); in tsi721_probe()
2839 priv->p2r_bar[0].size = pci_resource_len(pdev, BAR_2); in tsi721_probe()
2845 tsi_debug(INIT, &pdev->dev, in tsi721_probe()
2848 priv->p2r_bar[1].base = pci_resource_start(pdev, BAR_4); in tsi721_probe()
2849 priv->p2r_bar[1].size = pci_resource_len(pdev, BAR_4); in tsi721_probe()
2855 tsi_err(&pdev->dev, "Unable to obtain PCI resources"); in tsi721_probe()
2861 priv->regs = pci_ioremap_bar(pdev, BAR_0); in tsi721_probe()
2862 if (!priv->regs) { in tsi721_probe()
2863 tsi_err(&pdev->dev, "Unable to map device registers space"); in tsi721_probe()
2864 err = -ENOMEM; in tsi721_probe()
2868 priv->odb_base = pci_ioremap_bar(pdev, BAR_1); in tsi721_probe()
2869 if (!priv->odb_base) { in tsi721_probe()
2870 tsi_err(&pdev->dev, "Unable to map outbound doorbells space"); in tsi721_probe()
2871 err = -ENOMEM; in tsi721_probe()
2876 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { in tsi721_probe()
2877 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tsi721_probe()
2879 tsi_err(&pdev->dev, "Unable to set DMA mask"); in tsi721_probe()
2883 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32))) in tsi721_probe()
2884 tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); in tsi721_probe()
2886 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); in tsi721_probe()
2888 tsi_info(&pdev->dev, "Unable to set consistent DMA mask"); in tsi721_probe()
2903 tsi_info(&pdev->dev, in tsi721_probe()
2907 /* Set PCIe completion timeout to 1-10ms */ in tsi721_probe()
2912 * FIXUP: correct offsets of MSI-X tables in the MSI-X Capability Block in tsi721_probe()
2928 tsi_err(&pdev->dev, "BDMA initialization failed"); in tsi721_probe()
2929 err = -ENOMEM; in tsi721_probe()
2958 if (priv->regs) in tsi721_probe()
2959 iounmap(priv->regs); in tsi721_probe()
2960 if (priv->odb_base) in tsi721_probe()
2961 iounmap(priv->odb_base); in tsi721_probe()
2976 tsi_debug(EXIT, &pdev->dev, "enter"); in tsi721_remove()
2980 flush_work(&priv->idb_work); in tsi721_remove()
2981 flush_work(&priv->pw_work); in tsi721_remove()
2982 rio_unregister_mport(&priv->mport); in tsi721_remove()
2990 if (priv->regs) in tsi721_remove()
2991 iounmap(priv->regs); in tsi721_remove()
2992 if (priv->odb_base) in tsi721_remove()
2993 iounmap(priv->odb_base); in tsi721_remove()
2995 if (priv->flags & TSI721_USING_MSIX) in tsi721_remove()
2996 pci_disable_msix(priv->pdev); in tsi721_remove()
2997 else if (priv->flags & TSI721_USING_MSI) in tsi721_remove()
2998 pci_disable_msi(priv->pdev); in tsi721_remove()
3004 tsi_debug(EXIT, &pdev->dev, "exit"); in tsi721_remove()
3011 tsi_debug(EXIT, &pdev->dev, "enter"); in tsi721_shutdown()
3035 MODULE_DESCRIPTION("IDT Tsi721 PCIExpress-to-SRIO bridge driver");