1 // SPDX-License-Identifier: GPL-2.0+
6  * - When changing both duty cycle and period, we may end up with one cycle
13  * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16  * - Only produces "normal" output.
17  * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
27 #include <linux/pwm.h>
37 	WARN_ON(cycles < 2 || cycles - 2 > priv->max);  in xilinx_timer_tlr_cycles()
40 		return cycles - 2;  in xilinx_timer_tlr_cycles()
41 	return priv->max - cycles + 2;  in xilinx_timer_tlr_cycles()
52 		cycles = (u64)priv->max - tlr + 2;  in xilinx_timer_get_period()
56 				  clk_get_rate(priv->clk));  in xilinx_timer_get_period()
60  * The idea here is to capture whether the PWM is actually running (e.g.
62  * we don't cause a glitch. According to the data sheet, to enable the PWM we
65  * - Set both timers to generate mode (MDT=1)
66  * - Set both timers to PWM mode (PWMA=1)
67  * - Enable the generate out signals (GENT=1)
71  * - The timer must be running (ENT=1)
72  * - The timer must auto-reload TLR into TCR (ARHT=1)
73  * - We must not be in the process of loading TLR into TCR (LOAD=0)
74  * - Cascade mode must be disabled (CASC=0)
76  * If any of these differ from usual, then the PWM is either disabled, or is
103 	if (state->polarity != PWM_POLARITY_NORMAL)  in xilinx_pwm_apply()
104 		return -EINVAL;  in xilinx_pwm_apply()
108 	 * priv->max + 2. To enforce this we can reduce the cycles, but we may  in xilinx_pwm_apply()
113 	rate = clk_get_rate(priv->clk);  in xilinx_pwm_apply()
115 	period_cycles = min_t(u64, state->period, U32_MAX * NSEC_PER_SEC);  in xilinx_pwm_apply()
117 	period_cycles = min_t(u64, period_cycles, priv->max + 2);  in xilinx_pwm_apply()
119 		return -ERANGE;  in xilinx_pwm_apply()
122 	duty_cycles = min_t(u64, state->duty_cycle, U32_MAX * NSEC_PER_SEC);  in xilinx_pwm_apply()
124 	duty_cycles = min_t(u64, duty_cycles, priv->max + 2);  in xilinx_pwm_apply()
131 		duty_cycles = period_cycles - 1;  in xilinx_pwm_apply()
137 	regmap_read(priv->map, TCSR0, &tcsr0);  in xilinx_pwm_apply()
138 	regmap_read(priv->map, TCSR1, &tcsr1);  in xilinx_pwm_apply()
141 	regmap_write(priv->map, TLR0, tlr0);  in xilinx_pwm_apply()
142 	regmap_write(priv->map, TLR1, tlr1);  in xilinx_pwm_apply()
144 	if (state->enabled) {  in xilinx_pwm_apply()
146 		 * If the PWM is already running, then the counters will be  in xilinx_pwm_apply()
151 			regmap_write(priv->map, TCSR0, tcsr0 | TCSR_LOAD);  in xilinx_pwm_apply()
152 			regmap_write(priv->map, TCSR1, tcsr1 | TCSR_LOAD);  in xilinx_pwm_apply()
156 			regmap_write(priv->map, TCSR0, tcsr0);  in xilinx_pwm_apply()
157 			regmap_write(priv->map, TCSR1, tcsr1);  in xilinx_pwm_apply()
160 		regmap_write(priv->map, TCSR0, 0);  in xilinx_pwm_apply()
161 		regmap_write(priv->map, TCSR1, 0);  in xilinx_pwm_apply()
174 	regmap_read(priv->map, TLR0, &tlr0);  in xilinx_pwm_get_state()
175 	regmap_read(priv->map, TLR1, &tlr1);  in xilinx_pwm_get_state()
176 	regmap_read(priv->map, TCSR0, &tcsr0);  in xilinx_pwm_get_state()
177 	regmap_read(priv->map, TCSR1, &tcsr1);  in xilinx_pwm_get_state()
178 	state->period = xilinx_timer_get_period(priv, tlr0, tcsr0);  in xilinx_pwm_get_state()
179 	state->duty_cycle = xilinx_timer_get_period(priv, tlr1, tcsr1);  in xilinx_pwm_get_state()
180 	state->enabled = xilinx_timer_pwm_enabled(tcsr0, tcsr1);  in xilinx_pwm_get_state()
181 	state->polarity = PWM_POLARITY_NORMAL;  in xilinx_pwm_get_state()
187 	if (state->period == state->duty_cycle)  in xilinx_pwm_get_state()
188 		state->duty_cycle = 0;  in xilinx_pwm_get_state()
209 	struct device *dev = &pdev->dev;  in xilinx_pwm_probe()
210 	struct device_node *np = dev->of_node;  in xilinx_pwm_probe()
216 	/* If there are no PWM cells, this binding is for a timer */  in xilinx_pwm_probe()
217 	ret = of_property_read_u32(np, "#pwm-cells", &pwm_cells);  in xilinx_pwm_probe()
218 	if (ret == -EINVAL)  in xilinx_pwm_probe()
219 		return -ENODEV;  in xilinx_pwm_probe()
221 		return dev_err_probe(dev, ret, "could not read #pwm-cells\n");  in xilinx_pwm_probe()
232 	priv->map = devm_regmap_init_mmio(dev, regs,  in xilinx_pwm_probe()
234 	if (IS_ERR(priv->map))  in xilinx_pwm_probe()
235 		return dev_err_probe(dev, PTR_ERR(priv->map),  in xilinx_pwm_probe()
238 	ret = of_property_read_u32(np, "xlnx,one-timer-only", &one_timer);  in xilinx_pwm_probe()
241 				     "Could not read xlnx,one-timer-only\n");  in xilinx_pwm_probe()
244 		return dev_err_probe(dev, -EINVAL,  in xilinx_pwm_probe()
245 				     "Two timers required for PWM mode\n");  in xilinx_pwm_probe()
247 	ret = of_property_read_u32(np, "xlnx,count-width", &width);  in xilinx_pwm_probe()
248 	if (ret == -EINVAL)  in xilinx_pwm_probe()
252 				     "Could not read xlnx,count-width\n");  in xilinx_pwm_probe()
255 		return dev_err_probe(dev, -EINVAL,  in xilinx_pwm_probe()
257 	priv->max = BIT_ULL(width) - 1;  in xilinx_pwm_probe()
260 	 * The polarity of the Generate Out signals must be active high for PWM  in xilinx_pwm_probe()
265 	priv->clk = devm_clk_get_enabled(dev, "s_axi_aclk");  in xilinx_pwm_probe()
266 	if (IS_ERR(priv->clk))  in xilinx_pwm_probe()
267 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in xilinx_pwm_probe()
270 	ret = devm_clk_rate_exclusive_get(dev, priv->clk);  in xilinx_pwm_probe()
275 	chip->ops = &xilinx_pwm_ops;  in xilinx_pwm_probe()
278 		return dev_err_probe(dev, ret, "Could not register PWM chip\n");  in xilinx_pwm_probe()
284 	{ .compatible = "xlnx,xps-timer-1.00.a", },
292 		.name = "xilinx-pwm",
298 MODULE_ALIAS("platform:xilinx-pwm");
299 MODULE_DESCRIPTION("PWM driver for Xilinx LogiCORE IP AXI Timer");