180 static void configure_polarity(struct ehrpwm_pwm_chip *pc, int chan)  in configure_polarity()  argument
195 		if (pc->polarity[chan] == PWM_POLARITY_INVERSED)  in configure_polarity()
203 		if (pc->polarity[chan] == PWM_POLARITY_INVERSED)  in configure_polarity()
210 	ehrpwm_modify(pc->mmio_base, aqctl_reg, aqctl_mask, aqctl_val);  in configure_polarity()
220 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_config()  local
229 	c = pc->clk_rate;  in ehrpwm_pwm_config()
238 		c = pc->clk_rate;  in ehrpwm_pwm_config()
249 		if (pc->period_cycles[i] &&  in ehrpwm_pwm_config()
250 				(pc->period_cycles[i] != period_cycles)) {  in ehrpwm_pwm_config()
265 	pc->period_cycles[pwm->hwpwm] = period_cycles;  in ehrpwm_pwm_config()
277 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CLKDIV_MASK, tb_divval);  in ehrpwm_pwm_config()
284 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_PRDLD_MASK, TBCTL_PRDLD_SHDW);  in ehrpwm_pwm_config()
286 	ehrpwm_write(pc->mmio_base, TBPRD, period_cycles);  in ehrpwm_pwm_config()
289 	ehrpwm_modify(pc->mmio_base, TBCTL, TBCTL_CTRMODE_MASK,  in ehrpwm_pwm_config()
299 	ehrpwm_write(pc->mmio_base, cmp_reg, duty_cycles);  in ehrpwm_pwm_config()
310 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_set_polarity()  local
313 	pc->polarity[pwm->hwpwm] = polarity;  in ehrpwm_pwm_set_polarity()
320 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_enable()  local
337 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_enable()
340 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_enable()
343 	configure_polarity(pc, pwm->hwpwm);  in ehrpwm_pwm_enable()
346 	ret = clk_enable(pc->tbclk);  in ehrpwm_pwm_enable()
358 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_disable()  local
371 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_disable()
373 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_disable()
378 	ehrpwm_modify(pc->mmio_base, AQSFRC, AQSFRC_RLDCSF_MASK,  in ehrpwm_pwm_disable()
381 	ehrpwm_modify(pc->mmio_base, AQCSFRC, aqcsfrc_mask, aqcsfrc_val);  in ehrpwm_pwm_disable()
384 	clk_disable(pc->tbclk);  in ehrpwm_pwm_disable()
392 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_free()  local
400 	pc->period_cycles[pwm->hwpwm] = 0;  in ehrpwm_pwm_free()
451 	struct ehrpwm_pwm_chip *pc;  in ehrpwm_pwm_probe()  local
456 	chip = devm_pwmchip_alloc(&pdev->dev, NUM_PWM_CHANNEL, sizeof(*pc));  in ehrpwm_pwm_probe()
459 	pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_probe()
472 	pc->clk_rate = clk_get_rate(clk);  in ehrpwm_pwm_probe()
473 	if (!pc->clk_rate) {  in ehrpwm_pwm_probe()
480 	pc->mmio_base = devm_platform_ioremap_resource(pdev, 0);  in ehrpwm_pwm_probe()
481 	if (IS_ERR(pc->mmio_base))  in ehrpwm_pwm_probe()
482 		return PTR_ERR(pc->mmio_base);  in ehrpwm_pwm_probe()
485 	pc->tbclk = devm_clk_get(&pdev->dev, "tbclk");  in ehrpwm_pwm_probe()
486 	if (IS_ERR(pc->tbclk))  in ehrpwm_pwm_probe()
487 		return dev_err_probe(&pdev->dev, PTR_ERR(pc->tbclk), "Failed to get tbclk\n");  in ehrpwm_pwm_probe()
489 	ret = clk_prepare(pc->tbclk);  in ehrpwm_pwm_probe()
507 	clk_unprepare(pc->tbclk);  in ehrpwm_pwm_probe()
515 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_remove()  local
519 	clk_unprepare(pc->tbclk);  in ehrpwm_pwm_remove()
526 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_save_context()  local
530 	pc->ctx.tbctl = ehrpwm_read(pc->mmio_base, TBCTL);  in ehrpwm_pwm_save_context()
531 	pc->ctx.tbprd = ehrpwm_read(pc->mmio_base, TBPRD);  in ehrpwm_pwm_save_context()
532 	pc->ctx.cmpa = ehrpwm_read(pc->mmio_base, CMPA);  in ehrpwm_pwm_save_context()
533 	pc->ctx.cmpb = ehrpwm_read(pc->mmio_base, CMPB);  in ehrpwm_pwm_save_context()
534 	pc->ctx.aqctla = ehrpwm_read(pc->mmio_base, AQCTLA);  in ehrpwm_pwm_save_context()
535 	pc->ctx.aqctlb = ehrpwm_read(pc->mmio_base, AQCTLB);  in ehrpwm_pwm_save_context()
536 	pc->ctx.aqsfrc = ehrpwm_read(pc->mmio_base, AQSFRC);  in ehrpwm_pwm_save_context()
537 	pc->ctx.aqcsfrc = ehrpwm_read(pc->mmio_base, AQCSFRC);  in ehrpwm_pwm_save_context()
544 	struct ehrpwm_pwm_chip *pc = to_ehrpwm_pwm_chip(chip);  in ehrpwm_pwm_restore_context()  local
546 	ehrpwm_write(pc->mmio_base, TBPRD, pc->ctx.tbprd);  in ehrpwm_pwm_restore_context()
547 	ehrpwm_write(pc->mmio_base, CMPA, pc->ctx.cmpa);  in ehrpwm_pwm_restore_context()
548 	ehrpwm_write(pc->mmio_base, CMPB, pc->ctx.cmpb);  in ehrpwm_pwm_restore_context()
549 	ehrpwm_write(pc->mmio_base, AQCTLA, pc->ctx.aqctla);  in ehrpwm_pwm_restore_context()
550 	ehrpwm_write(pc->mmio_base, AQCTLB, pc->ctx.aqctlb);  in ehrpwm_pwm_restore_context()
551 	ehrpwm_write(pc->mmio_base, AQSFRC, pc->ctx.aqsfrc);  in ehrpwm_pwm_restore_context()
552 	ehrpwm_write(pc->mmio_base, AQCSFRC, pc->ctx.aqcsfrc);  in ehrpwm_pwm_restore_context()
553 	ehrpwm_write(pc->mmio_base, TBCTL, pc->ctx.tbctl);  in ehrpwm_pwm_restore_context()