drivers/pwm/pwm-sunplus.c

1 // SPDX-License-Identifier: GPL-2.0
3  * PWM device driver for SUNPLUS SP7021 SoC
7  *   https://sunplus-tibbo.atlassian.net/wiki/spaces/doc/overview
9  *   Reference Manual(PWM module):
10  *   https://sunplus.atlassian.net/wiki/spaces/doc/pages/461144198/12.+Pulse+Width+Modulation+PWM
13  * - Only supports normal polarity.
14  * - It output low when PWM channel disabled.
15  * - When the parameters change, current running period will not be completed
17  * - In .apply() PWM output need to write register FREQ and DUTY. When first write FREQ
23 #include <linux/clk.h>
29 #include <linux/pwm.h>
47 	struct clk *clk;  member
55 static int sunplus_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,  in sunplus_pwm_apply()  argument
62 	if (state->polarity != pwm->state.polarity)  in sunplus_pwm_apply()
63 		return -EINVAL;  in sunplus_pwm_apply()
65 	if (!state->enabled) {  in sunplus_pwm_apply()
66 		/* disable pwm channel output */  in sunplus_pwm_apply()
67 		mode0 = readl(priv->base + SP7021_PWM_MODE0);  in sunplus_pwm_apply()
68 		mode0 &= ~SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);  in sunplus_pwm_apply()
69 		writel(mode0, priv->base + SP7021_PWM_MODE0);  in sunplus_pwm_apply()
70 		/* disable pwm channel clk source */  in sunplus_pwm_apply()
71 		mode1 = readl(priv->base + SP7021_PWM_MODE1);  in sunplus_pwm_apply()
72 		mode1 &= ~SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);  in sunplus_pwm_apply()
73 		writel(mode1, priv->base + SP7021_PWM_MODE1);  in sunplus_pwm_apply()
77 	clk_rate = clk_get_rate(priv->clk);  in sunplus_pwm_apply()
80 	 * The following calculations might overflow if clk is bigger  in sunplus_pwm_apply()
85 		return -EINVAL;  in sunplus_pwm_apply()
88 	 * With clk_rate limited above we have dd_freq <= state->period,  in sunplus_pwm_apply()
91 	dd_freq = mul_u64_u64_div_u64(clk_rate, state->period, (u64)SP7021_PWM_FREQ_SCALER  in sunplus_pwm_apply()
95 		return -EINVAL;  in sunplus_pwm_apply()
100 	writel(dd_freq, priv->base + SP7021_PWM_FREQ(pwm->hwpwm));  in sunplus_pwm_apply()
102 	/* cal and set pwm duty */  in sunplus_pwm_apply()
103 	mode0 = readl(priv->base + SP7021_PWM_MODE0);  in sunplus_pwm_apply()
104 	mode0 |= SP7021_PWM_MODE0_PWMEN(pwm->hwpwm);  in sunplus_pwm_apply()
105 	mode1 = readl(priv->base + SP7021_PWM_MODE1);  in sunplus_pwm_apply()
106 	mode1 |= SP7021_PWM_MODE1_CNT_EN(pwm->hwpwm);  in sunplus_pwm_apply()
107 	if (state->duty_cycle == state->period) {  in sunplus_pwm_apply()
108 		/* PWM channel output = high */  in sunplus_pwm_apply()
109 		mode0 |= SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);  in sunplus_pwm_apply()
110 		duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | SP7021_PWM_DUTY_MAX;  in sunplus_pwm_apply()
112 		mode0 &= ~SP7021_PWM_MODE0_BYPASS(pwm->hwpwm);  in sunplus_pwm_apply()
116 		duty = mul_u64_u64_div_u64(state->duty_cycle, clk_rate,  in sunplus_pwm_apply()
118 		duty = SP7021_PWM_DUTY_DD_SEL(pwm->hwpwm) | duty;  in sunplus_pwm_apply()
120 	writel(duty, priv->base + SP7021_PWM_DUTY(pwm->hwpwm));  in sunplus_pwm_apply()
121 	writel(mode1, priv->base + SP7021_PWM_MODE1);  in sunplus_pwm_apply()
122 	writel(mode0, priv->base + SP7021_PWM_MODE0);  in sunplus_pwm_apply()
127 static int sunplus_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,  in sunplus_pwm_get_state()  argument
134 	mode0 = readl(priv->base + SP7021_PWM_MODE0);  in sunplus_pwm_get_state()
136 	if (mode0 & BIT(pwm->hwpwm)) {  in sunplus_pwm_get_state()
137 		clk_rate = clk_get_rate(priv->clk);  in sunplus_pwm_get_state()
138 		dd_freq = readl(priv->base + SP7021_PWM_FREQ(pwm->hwpwm));  in sunplus_pwm_get_state()
139 		duty = readl(priv->base + SP7021_PWM_DUTY(pwm->hwpwm));  in sunplus_pwm_get_state()
145 		state->period = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)SP7021_PWM_FREQ_SCALER  in sunplus_pwm_get_state()
150 		state->duty_cycle = DIV64_U64_ROUND_UP((u64)dd_freq * (u64)duty * NSEC_PER_SEC,  in sunplus_pwm_get_state()
152 		state->enabled = true;  in sunplus_pwm_get_state()
154 		state->enabled = false;  in sunplus_pwm_get_state()
157 	state->polarity = PWM_POLARITY_NORMAL;  in sunplus_pwm_get_state()
169 	struct clk *clk = data;  in sunplus_pwm_clk_release()  local
171 	clk_disable_unprepare(clk);  in sunplus_pwm_clk_release()
176 	struct device *dev = &pdev->dev;  in sunplus_pwm_probe()
186 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in sunplus_pwm_probe()
187 	if (IS_ERR(priv->base))  in sunplus_pwm_probe()
188 		return PTR_ERR(priv->base);  in sunplus_pwm_probe()
190 	priv->clk = devm_clk_get(dev, NULL);  in sunplus_pwm_probe()
191 	if (IS_ERR(priv->clk))  in sunplus_pwm_probe()
192 		return dev_err_probe(dev, PTR_ERR(priv->clk),  in sunplus_pwm_probe()
193 				     "get pwm clock failed\n");  in sunplus_pwm_probe()
195 	ret = clk_prepare_enable(priv->clk);  in sunplus_pwm_probe()
201 	ret = devm_add_action_or_reset(dev, sunplus_pwm_clk_release, priv->clk);  in sunplus_pwm_probe()
207 	chip->ops = &sunplus_pwm_ops;  in sunplus_pwm_probe()
211 		return dev_err_probe(dev, ret, "Cannot register sunplus PWM\n");  in sunplus_pwm_probe()
217 	{ .compatible = "sunplus,sp7021-pwm", },
225 		.name	= "sunplus-pwm",
231 MODULE_DESCRIPTION("Sunplus SoC PWM Driver");